參數(shù)資料
型號(hào)： SI3225PPTX-EVB
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 87/112頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL W/DISCRETE INTERFACE
設(shè)計(jì)資源： Si3225PPTX-EVB Schematics/Layout
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3225
已供物品： 板，CD
Si3220/25 Si3200/02
76
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
In Figure 42, the CID field is zero. As this field is
decremented (in LSB to MSB order), the value
decrements for each SDI down the line. The BRDCST,
R/W, and REG/RAM bits remain unchanged as the
control word passes through the entire chain. The odd
SDIs are internal to the device and represent the SDI to
SDI_THRU connection between channels of the same
device. A unique CID is presented to each channel, and
the channel receiving a CID value of zero is the target of
the operation (channel 0 in this case). The last line of
Figure 42 illustrates that in Broadcast mode, all bits
pass through the chain without permutation.
Figures 43 and 44 illustrate WRITE and READ
operations to register addresses via an 8-bit SPI
controller. These operations are performed as a 3-byte
transfer. CS is asserted between each byte, which is
required for CS to be asserted before the first falling
edge of SCLK after the DATA byte to indicate to the
state machine that one byte only should be transferred.
The state of SDI is a “don’t care” during the DATA byte
of a read operation.
Figure 42. Sample SPI Control Word to Address Channel 0
Figure 43. Register Write Operation via an 8-Bit SPI Port
Figure 44. Register Read Operation via an 8-Bit SPI Port
SPI Control Word
BRDCST
R/W
REG/RAM
Reserved
CID[0]
CID[1]
CID[2]
CID[3]
0
A
B
C
0
A
B
C
1
0
A
B
C
0
1
0
A
B
C
1
0
1
0
A
B
C
0
1
0
A
B
C
1
0
1
A
B
C
D
E
F
G
SDI0
SDI1 (Internal)
SDI2
SDI3 (Internal)
SDI 14
SDI15 (Internal)
SDI0-15
CONTROL
ADDRESS
DATA [7:0]
SCLK
SDI
SDO
Hi-Z
CS
CONTROL
ADDRESS
X X X X X X X X
CS
SCLK
SDI
SDO
Data [7:0]
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