(V
參數(shù)資料
型號: SI3225PPTX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 23/112頁
文件大小: 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
設(shè)計資源: Si3225PPTX-EVB Schematics/Layout
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3225
已供物品: 板,CD
Si3220/25 Si3200/02
18
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
Table 13. Switching Characteristics—PCM Highway Interface
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF)
Parameter
Symbol
Test
Conditions
Min1
Typ1
Max1
Units
PCLK Period
tp
122
3906
ns
Valid PCLK Inputs
256
512
768
1.024
1.536
1.544
2.048
4.096
8.192
kHz
MHz
FSYNC Period2
tfs
—125
s
PCLK Duty Cycle Tolerance
tdty
40
50
60
%
PCLK Period Jitter Tolerance
tjitter
±120
ns
Rise Time, PCLK
tr
25
ns
Fall Time, PCLK
tf
25
ns
Delay Time, PCLK Rise to DTX Active
td1
20
ns
Delay Time, PCLK Rise to DTX
Transition
td2
20
ns
Delay Time, PCLK Rise to DTX Tri-
state3
td3
20
ns
Setup Time, FSYNC to PCLK Fall
tsu1
25
ns
Hold Time, FSYNC to PCLK Fall
th1
20
ns
Setup Time, DRX to PCLK Fall
tsu2
25
ns
Hold Time, DRX to PCLK Fall
th2
20
ns
FSYNC Pulse Width
twfs
tp/2
125 s–tp
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4 V, VIL = 0.4 V.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
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