Table 10. DC Characteristics (VDD<" />
參數(shù)資料
型號: SI3225PPTX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 21/112頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
設(shè)計資源: Si3225PPTX-EVB Schematics/Layout
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3225
已供物品: 板,CD
Si3220/25 Si3200/02
16
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
Table 10. DC Characteristics (VDD, VDD1–VDD4 = 3.3 V)
(VDD, VDD1 – VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
0.7 x VDD
—5.25
V
Low Level Input Voltage
VIL
0.3 x VDD
V
High Level Output
Voltage
VOH
IO =4mA
VDD –0.6
V
Low Level Output
Voltage
VOL
DTX, SDO, INT,
SDITHRU:
IO =–4mA
——
0.4
V
BATSELa/b, RRDa/b,
GPOa/b, TRD1a/b, TRD2a/b:
IO =–40 mA
——
0.72
SDITHRU internal pullup
resistance
35
50
k
Relay Driver Source Imped-
ance
ROUT
VDD1–VDD4 =3.13V
IO < 28 mA
—63
Relay Driver Sink Impedance
RIN
VDD1–VDD4 =3.13V
IO < 85 mA
—11
Input Leakage Current
IL
——
±10
A
Table 11. Switching Characteristics—General Inputs1
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Rise Time, RESET
tr
——
5
ns
RESET Pulse Width, GCI Mode2
trl
500
ns
RESET Pulse Width, SPI Daisy Chain Mode
trl
6—
s
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VDD
0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 k
per device.
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