參數(shù)資料
型號(hào)： T8105A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁(yè)數(shù)： 107/112頁(yè)
文件大?。?/td> 1408K
代理商： T8105A
Lucent Technologies Inc.
103
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
Appendix B. Minimum Delay and
Constant Delay Connections
B.1 Connection Definitions
Forward
Connection
A forward connection is defined as one
in which the output (
to
) time slot has a
greater value than the input (
from
) time
slot, or put another way, the delta
between them is positive.
A reverse connection is defined as one
in which the output (
to
) time slot has a
lesser value than the input (
from
) time
slot, and the delta between them is
negative.
Reverse
Connection
So, for example, going from TS(1) to TS(38) is a for-
ward connection, and the TS
is +37, but going from
TS(38) to TS(1) is a reverse connection, with a TS
of
–37:
where TS
= TS(
to
) – TS(
from
).
Similarly, a delta can be introduced for streams which
will have a bearing in certain exceptions (discussed
later):
STR
= STR(
to
) – STR(
from
)
There is only one combination which forms a TS
of
+127 or –127:
TS
= TS(127) – TS(0) = +127, and
TS
= TS(0) – TS(127) = –127,
but there are two combinations which form TS
s of
+126 or –126:
TS
= TS(127) – TS(1) = TS(126) – TS(0) = +126, and
TS
= TS(1) – TS(127) = TS(0) – TS(126) = –126,
there are three combinations which yield +125 or –125,
and so on.
The user can utilize the TS
to control the latency of
the resulting connection. In some cases, the latency
must be minimized. In other cases, such as a block of
connections which must maintain some relative integ-
rity while crossing a frame boundary, the required
latency of some of the connections may exceed one
frame (>128 time slots) to maintain the integrity of this
virtual frame.
Each device contains several bits for controlling
latency. Each connection has a bit which is used for
selecting one of two alternating data buffers. These bits
are set in the local connection memory (T8100A,
T8105 only) for local switching or in the tag register
field of the CAM section for H-bus switching. There are
also 2 bits in the CON register, address 0x0E, which
can control the buffer selection on a chip-wide basis.
Bit 1 of the register overrides the indiv idual FME bits.
Bit 0 becomes the global, chip-wide, FME setting.
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