參數(shù)資料
型號(hào)： T8105A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁(yè)數(shù)： 55/112頁(yè)
文件大?。?/td> 1408K
代理商： T8105A
Lucent Technologies Inc.
51
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.5 Clocking Section
(continued)
2.5.8 Clock Control Register Definitions
(continued)
Table 48. CKP: Clocks, Programmable Outputs, 0x02
Clock register 0x02, CKP is the programmed clocks register. It is used for programming the CT_C8 clocks and
enabling its outputs. It is also used to program the TCLK selector. CT_C8 may be operated as either 8 MHz (nor-
mal or inverted) or 4 MHz (normal or inverted). C8IS is used to invert the synchronization on C8A and C8B when
they are selected for input. The C8 and FRAME signals, which are also generated internally, are routed to both the
CT_C8A and /CT_FRAMEA and to the CT_C8B and /CT_FRAMEB. The CAE and CBE pins enable these output
pairs independently. The C8C4 pin selects 8.192 MHz or 4.096 MHz signals to be output on C8A and C8B (for sup-
porting for either ECTF or MC-1 applications). CFW selects the output width of the compatibility frame. The register
format is as follows.
Reg
CKP
R/W
—
Bit 7
Bit 6
PTS
Bit 5
Bit 4
C8IS
Bit 3
CAE
Bit 2
CBE
Bit 1
C8C4
Bit 0
CFW
Symbol
PTS
Bit
7—5 The three PTS bits select the output sent to the TCLK. This output is intended to be used for
driving framers.
PTS = 000,
3-state.
PTS = 001,
Oscillator, buffered output.
PTS = 010,
PLL #2, direct output .
PTS = 011,
PLL #2, output divided by 2.
PTS = 100,
2.048 MHz from state machines.
PTS = 101,
4.096 MHz from state machines.
PTS = 110,
8.192 MHz from state machines.
PTS = 111,
16.384 MHz from state machines.
4
C8IS = 0,
MC-1 (A and B clocks inputs interpreted as /C4 with /FRAME).
C8IS = 1,
ECTF (A and B clocks inputs interpreted as C8 with /FRAME).
3
CAE = 0,
Disable CT_C8A & /CT_FRAMEA outputs.
CAE = 1,
Enable CT_C8A & /CT_FRAMEA outputs. (The devices will auto-
matically disable these on an A clock failure.)
2
CBE = 0,
Disable CT_C8B & /CT_FRAMEB outputs.
CBE = 1,
Enable CT_C8B & /CT_FRAMEB outputs. (The devices will auto-
matically disable these on a B clock failure.)
1
C8C4 = 0,
Inverted 4.096 MHz (MC-1 output mode).
C8C4 = 1,
Noninverted 8.192 MHz (ECTF output mode).
0
CFW = 0,
Narrow (122 ns) /FR_COMP
CFW = 1,
Wide (244 ns) /FR_COMP
Description
C8IS
CAE
CBE
C8C4
CFW
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