參數(shù)資料
型號(hào): T8105A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時(shí)隙Interchangers
文件頁(yè)數(shù): 22/112頁(yè)
文件大?。?/td> 1408K
代理商: T8105A
18
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional
Description
(continued)
2.1 Register/Memory Maps
(continued)
2.1.4 Control Register Memory Space
(continued)
This section is a summary of the register functions. The
reader is encouraged to read through the rest of this
specification to learn the details of the individual regis-
ters and their interactions with the overall architecture.
Table 12. CKM: Clocks, Main Clock Selection, 0x00
Table 13. CKN: Clocks, NETREF Selections, 0x01
Table 14. CKP: Clocks, Programmable Outputs,
0x02
Table 15. CKR: Clocks, Resource Selection, 0x03
Table 16. CKS: Clocks, Secondary (Fallback)
Selection, 0x04
Table 17. CK32: Clocks, Locals 3 and 2, 0x05
Table 18. CK10: Clocks, Locals 1 and 0, 0x06
Bit
7
6
5
4
3
2
1
0
Description
Phase Alignment Enable
Phase Alignment Select
Compatibility Clock Direction
Input Clock Invert
Input Clock Select, MSB
Input Clock Select
Input Clock Select
Input Clock Select, LSB
Bit
7
6
5
4
3
2
1
0
Description
NETREF1 Output Enable
NETREF2 Output Enable
Bypass Select
Input Clock Invert
Input Clock Select, MSB
Input Clock Select
Input Clock Select
Input Clock Select, LSB
Bit
7
6
5
4
3
2
1
0
Description
TCLK Select, MSB
TCLK Select
TCLK Select, LSB
CT_C8 Pins, Input Type Select
CT_C8A Output Enable
CT_C8B Output Enable
CT_C8 Pins, Output Type Select
/FR_COMP Pulse Width
Bit
7
6
5
4
3
2
1
0
Description
Resource Select, MSB
Resource Select, LSB
PLL #1 Bypass
PLL #1 Rate Select
PLL #2 Bypass
PLL #2 Rate Select
SCLK Output Select, MSB
SCLK Output Select, LSB
Bit
7
6
5
4
3
2
1
0
Description
Secondary Resource Select, MSB
Secondary Resource Select, LSB
Fallback Type Select, MSB
Fallback Type Select, LSB
Fallback, Force Selection of Secondary Input
Secondary Input Clock Select, MSB
Secondary Input Clock Select
Secondary Input Clock Select, LSB
Bit
7
6
5
4
3
2
1
0
Description
Local Clock 3 Select, MSB
Local Clock 3 Select
Local Clock 3 Select
Local Clock 3 Select, LSB
Local Clock 2 Select, MSB
Local Clock 2 Select
Local Clock 2 Select
Local Clock 2 Select, LSB
Bit
7
6
5
4
3
2
1
0
Description
Local Clock 1 Select, MSB
Local Clock 1 Select
Local Clock 1 Select
Local Clock 1 Select, LSB
Local Clock 0 Select, MSB
Local Clock 0 Select
Local Clock 0 Select
Local Clock 0 Select, LSB
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