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| 型號： | T8105A |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchangers |
| 中文描述： | H.100/H.110接口和時隙Interchangers |
| 文件頁數(shù)： | 33/112頁 |
| 文件大小： | 1408K |
| 代理商： | T8105A |
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Lucent Technologies Inc.
29
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.2 Local Bus Section
(continued)
2.2.5 State Counter Operation
All operations are synchronized to the master state counter. The state counter is, in turn, synchronized to the inter-
nal frame signal and driven by an internal 65.536 MHz clock. In normal operation, the internal frame and clock are
synchronized to either the H-bus or trunks (see Section 2.5 Clocking Section for a more detailed explanation of
clocking options). The local memory states (T8100A, T8105 only) are illustrated in Figure 8. The state counter is a
modulo-8192 counter (7 bits for time slot, 4 bits for stream, 2 bits for state function) which can also be reset and
loaded with other values for diagnostic purposes (as described in Section 2.9 Testing and Diagnostics). The H-bus
memories are also referenced to this state counter so that the devices maintain synchronization with the H-bus to
ensure proper access to the bus as well as ensure synchronization between the H-bus and local memory struc-
tures. The H-bus memories are discussed in Section 2.3 H-Bus Section.
5-6107F
Figure 8. Simplified Local Memory State Timing, 65.536 MHz Clock
2.2.6 Software to Reset the Local Connection Memory
When the device is powered up, random connections may exist. To clear the upper 6 bits and, therefore, all control
bits, the following sequence of instructions should be followed:
1. Write AMR = 0x00.
2. Write LAR = 0x30.
3. Write IDR = 0x0C.
4. Monitor Diag-1, 0x30, bit 0. This bit is set when the operation is complete (steps 1 through 3).
5. Write LAR = 0x30.
6. Write IDR = 0x00. This brings the device out of diagnostics mode.
After executing the instructions, the contents of the local connection memory will contain its corresponding 10-bit
address. The upper 6 bits are cleared to zero. The lower 10 bits will have an address.
61 ns
L0
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
976 ns
CONNECTION
MEMORY
H6 READ
MICROPROCESSOR
DATA
SRAM
CLOCK
H6 WRITE
H6 READ
MICRO-
PRO-
CESSOR
MICRO-
PRO-
CESSOR
15.25 ns
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| T810-600B-TR | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB |
| T810-600G | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB |
| T810-600G-TR | 功能描述:雙向可控硅 8.0 Amp 600 Volt RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB |
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