參數(shù)資料
型號: T8105A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時隙Interchangers
文件頁數(shù): 83/112頁
文件大?。?/td> 1408K
代理商: T8105A
Lucent Technologies Inc.
79
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
3 Using the TSI Devices
(continued)
3.4 Using the LAR, AMR, and IDR for Connections
(continued)
3.4.3 Programming Examples
(continued)
;**Secondary Controls (Fallback)
MD,IDR,35h
;Enable ECTF Fallback: Become the new A Clock master on A
Clock failure,
;synchronizes to a bit clock on local reference 1, but
requires the main divider
;with external input (assumes a CLAD is between the
divider and 4MHzIn).
;Move the data to CKS
;Set up Main divider with divide-by-256
;Move the data to divider
;
MI,CKS,IDR
MD,IDR,0FFh
MI,CKMD,IDR
;**Local Clocks
MD,IDR,0E4h
;Local Selected Clock 3 gets inverted 8.192 MHz, LSC2 gets
2.048 MHz
;Move it to CK32
;LSC1 is high & LSC0 is low
;Move it to CK10
MI,CK32,IDR
MD,IDR,80h
MI,CK10,IDR
;
;*******Set up Local Streams
;
MD,IDR,30h
MI,LBS,IDR
;
;*******Set up H Bus Streams
;
MD,IDR,0AAh
MI,HSL,IDR
;
MD,IDR,0FFh
MI,HSH,IDR
;8 Streams at 8 Mbits/s
;Define input streams per IDR
;Define H-Bus Streams 0 - 15 for 4 Mbits/s
;Do it
;Define H-Bus Streams 16-31 for 8 Mbits/s
;Engage
;*******Set up Framers
;
MD,IDR,00h
MI,FRLA,IDR
MI,FRLB,IDR
MI,FRPH,IDR
MD,IDR,0F0h
MI,FRHA,IDR
MD,IDR,0F4h
MI,FRHB,IDR
;This sequence sets up Group A
;
to start coincident
;
with the Frame
;
boundary and Group B
;
to start halfway through
;
the Frame. The Groups
;
operate in normal framing mode
;
at 8 Mbits/s and are Double Byte wide.
;Note: FRPH sets up the correct routing.
;
;*******Connect the devices to the outside world
;
MD,MCR,0Eh
;
Enable H-Bus Streams & Clock, Local Streams,
local
Clocks including Framers
;
;
;*******END OF EXAMPLE #1
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