參數(shù)資料
型號: T8105A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時隙Interchangers
文件頁數(shù): 92/112頁
文件大?。?/td> 1408K
代理商: T8105A
88
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
4 Electrical Characteristics
(continued)
4.8 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)
(continued)
4.8.5 Detailed Clock Skew Diagram
5-6122F
Figure 27. Detailed Clock Skew Diagram
4.8.6 ac Electrical Characteristics, Skew Timing, H-Bus (H.100 Spec., Rev. 1.0)
Table 77. ac Electrical Characteristics, Skew Timing, H-Bus (H.100 Spec., Rev. 1.0)
1. Test load—50 pF.
2. Assumes A and B masters in adjacent slots.
3. When static skew is 10 ns and, in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum
skew of 30 ns will occur during that clock cycle.
4. Meeting the skew requirements in Table 10 and the requirements of Section 2.3 H-Bus Section could require the PLLs generating CT_C8 to
have different time constants when acting as primary and secondary clock masters.
Symbol
tSKC8
tSKCOMP Maximum Skew Between CT_C8_A and Any
Compatibility Clock
Maximum Skew Between CT_C8_A and L_SCx Clock
Parameter
Min
Typ
Max
±10, ±
Φ
±5
Unit
ns
ns
Notes
1, 2, 3, 4
1
Maximum Skew Between CT_C8 A and B
±2
ns
1
Vt+
Vt+
CT_C8_A
CT_C8_B
tSKC8
Vt+
Vt+
CT_C8_A
COMPATIBILITY
CLOCKS
tSKCOMP
Vt–
tSKCOMP
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