參數(shù)資料
型號(hào)： T8105A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁(yè)數(shù)： 60/112頁(yè)
文件大?。?/td> 1408K
代理商： T8105A
56
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.5 Clocking Section
(continued)
2.5.8 Clock Control Register Definitions
(continued)
2.5.8.2 CKMD, CKND, CKRD: Clocks, Main, NETREF, Resource Dividers, 0x07, 0x08, and 0x09
(continued)
The CON register controls various features of the device. It has a bit for enabling/disabling the use of the GPD reg-
ister and a bit for selecting NETREF_1 or NETREF_2. It also has 3 bits for using the L_REF pairing feature. The
last 2 bits are programmed when using the minimum and constant delay settings for data transfers. The description
and use of the bit(s) for a particular feature is described in the section which pertains to the feature.
Table 52. CON Register 0x0E
Reg
CON
R/W
—
Bit 7
RES
Bit 6
GPDENB
Bit 5
NETSEL
Bit 4
Bit 3
LREFIFS
Bit 2
LREFIBC
Bit 1
CED
Bit 0
GFME
LREFENB
Symbol
Reserved
GPDENB
Bit
7
6
Description
Reserved.
0: Disables the GPD register.
1: Enables the GPD register.
0: Select NETREF_1.
1: Select NETREF_2.
0: LREF’s are 8 unsynchronized inputs.
1: LREF’s are 4 pairs of synchronized inputs.
0: LREF frame strobe is not inverted.
1: LREF frame strobe is inverted.
0: LREF bit clock is not inverted.
1: LREF bit clock is inverted.
0: Individual FME bits are used for all transfers.
1: Value of GFME (CON register bit 0) is used for all transfers.
0: Only reverse connections provide constant delay.
1: Only forward connections provide constant delay.
NETSEL
5
LREFENB
4
LREFIFS
3
LREFIBC
2
CED
1
GFME
0
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