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參數(shù)資料
| 型號： | T8105A |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchangers |
| 中文描述： | H.100/H.110接口和時隙Interchangers |
| 文件頁數(shù)： | 79/112頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | T8105A |
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Lucent Technologies Inc.
75
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
3 Using the TSI Devices
(continued)
3.4 Using the LAR, AMR, and IDR for Connections
(continued)
3.4.2 Setting Up H-Bus Connections
Table 71. IDR: Indirect Data Register, H-Bus Connections Only
The CAM blocks are 512 locations each (T8102, T8105 only) and the operations for the CAM blocks are selected
by AMR (see Section 2.1.3 Address Mode Register and Section 2.3.2 CAM Operation and Commands). Since the
block address is carried in the AMR, this reduces the number of bits that are necessary to establish a connection.
Eleven (11) address bits, i.e., bits for stream and time-slot identification, the 8-bit tag (pointer to the H-bus data
memory), and 3 control bits all need to be written into the selected CAM block for setting up a connection. (The
empty bit is a status bit that is changed internally as a result of operations on the CAM.) Four* transfers, indirect
writes through the IDR, are required to set up a connection in the CAM, though the method of transfer is different
than with the local memory. Since a specific physical address is not always necessary, the CAM will automatically
fill the first available slot. Thus, the LAR is not required for setting up the connection. (See the notes below.) The
first transfer after programming the AMR requires that the 7 bits which identify the time-slot number (refer to Sec-
tion 2.3.5 H-Bus Rate Selection and Connection Address Format for the proper format) be loaded into the IDR. The
second transfer uses a similar field description for the IDR as presented for local connections [Section 3.4.1 Setting
Up Local Connections (T8100A, T8105 Only) above]. The address field contains the stream number (5 bits), and
the control field contains only 3 control bits.
The third transfer for CAM connection setup is the transfer of the lower 8 bits of the tag field. The tag is loaded into
the IDR. The fourth transfer is the subrate control field and the TAG field MSB. The connection for the CAM is actu-
ally set up, (i.e., the memory access takes place) using a fifth write. It is an indirect write to the AMR (again through
the IDR) which corresponds with the specific command and blocks the user requests. All CAM commands require
that the IDR be loaded with the same command value as the AMR rather than a don’t care or dummy value.
Notes:
If an address is to be matched, such as the break connection command, then only the first two transfers
are required. The tag is unnecessary for identifying a connection.
The LAR is only used to read or query a specific location (i.e., 0—511) in a particular CAM block. Refer to
Section 2.1.3 Address Mode Register and Section 2.3.2 CAM Operation and Commands for details on
these commands.
For the CAMs, pattern mode is a 1/2 connection. Only the intended output to the H-bus (or to the local pins) needs
to be specified. The setup is the same as described above, four transfers to the holding registers followed by the
make connection command to the appropriate CAM block. When the address is matched, the tag value (from the
pipeline SRAM) will be sent as output to the bus
.
* Four transfers are required for the T8105 and T8102. For the T8100A, if subrate is enabled, then four transfers are also required. If subrate is
disabled, only three transfers are required and the T8100A follows the same programming model as the T8100.
Two subsequent IDR reads are required to retrieve the 9-bit physical address for the T8105 and T8102. Only one IDR read is required to
retrieve the 8-bit physical address for the T8100A.
Reg
IDR
R/W
—
Bit 7
Bit 6
Control
PME
Bit 5
Bit 4
Bit 3
Bit 2
Address
—
Bit 1
Bit 0
R/W
FME
—
—
—
—
Symbol
R/W
Bit
7
Description
Refers to the direction in the CAM data memory. A read sends data to the bus; a write loads
data from the bus.
Pattern mode enable, similar to above, except the tag byte is output instead of the lower address
bits.
Data buffer selection for setting delay type. (Refer to Appendix B for minimum and constant
delay settings.)
4—0 All 5 bits are used for the stream address of the desired data memory location.
PME
6
FME
5
Address
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| T810-600B-TR | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB |
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