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參數(shù)資料
| 型號： | THS8200PFPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | GREEN, PLASTIC, HTQFP-80 |
| 文件頁數(shù)： | 20/101頁 |
| 文件大小： | 806K |
| 代理商： | THS8200PFPG4 |
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4–10
Figure 4–5 and Figure 4–6 also show the analog output from the DAC if the full-scale video range over the [64..940]
input would correspond to the normal 700 mV range for component video. This full-scale range is set by the selected
FSADJ full-scale setting (register data_fsadj).
4.5.3
Multiplying
When the 10-bit range is not fully used for video, we can scale the input video data to use the full 10-bit dynamic range
of the DACs. Care should be taken not to over/underflow the available range after scaling.
This multiplying control serves two purposes:
Use of the full 10-bit DAC range for inputs of reduced range
Individual fine gain control per channel to compensate for gain errors and provide white balance control
1023
964
817.3 mV
770.0 mV
255
767
511
0
Input Digital Codes
Analog
Output
From
DACs
Ramping Analog Output With 1:1.1 AC Range Fine Scaling
Range After
Scaling Up 1:1.1
700.0 mV
876
DC Shifted
Original AC Range
Figure 4–7. Effect of Scaling the Analog Video Output
Figure 4–7 illustrates a shifted analog ramping output. The multiplication factor could be calculated to scale this
output range to the full 10-bit range of the DAC. Note that this scaling can be programmed individually per channel
using registers csm_mult_<gy,rcr,bcb>. The range of the multiplication is 0..1.999, coded as a binary weighted 11-bit
value, thus: csm_mult_<gy,rcr,bcb> = (Desired scale ( 0 to 1.999) / 1.999)
× 2047
Note that this approach allows to scale input code ranges that are different on each channel to an identical full-scale
DAC output compliance, as is required for ITU-R.BT601 sampled signals where Y video data is represented in the
range [64..940] and both Cb,Cr color difference channels are coded within the range [64..960]. All three channels
need to generate a 700-mV nominal analog output compliance. Using a combination of FSADJ—adjusting the
full-scale current of all DAC channels simultaneously in the analog domain—and digital CSM control, different
trade-offs can be made for DAC output amplitude control, including channel matching.
As discussed in Display Timing Generator (Section 4.7), the user also controls the DAC output levels during blanking,
negative and positive sync, pre- and post-equalization, and serration pulses. Using a combination of CSM and DTG
programming, it is therefore possible to accommodate many video standards, including those that require a video
blank-to-black level setup, as well as differing video/sync ratios (e.g., 10:4 or 7:3).
Finally, using the selectable full-scale adjustment from the FSADJ1 or FSADJ2 terminals, it is possible to switch
between two analog output compliance settings with no hardware changes.
Physically, the CSM output is represented internally as an 11-bit value to improve the DAC linearity at the 10-bit level
after scaling. Each DAC internally is of 11-bit resolution.
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