參數(shù)資料
型號： THS8200PFPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： GREEN, PLASTIC, HTQFP-80
文件頁數(shù)： 88/101頁
文件大?。?/td> 806K
代理商： THS8200PFPG4
7–4
7.3.3
Analog (DAC) Outputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC resolution
10
(11 bit internal)
10
(11 bit internal)
bits
INL
Integral nonlinearity
Best-fit
VDD_IO =
Video (0.7 + 0.35 V
bias)
+0.5/–1.2
+2/–2
LSB
INL
Integral nonlinearity
VDD_IO =
3.3 V, CLK =
500 kHz
Generic (1.25 + 0 V
bias)
+1/–2.1
+5/–5
LSB
DNL
Differential nonlinearity
VDD_IO =
3 3 V CLK
Video (0.7 + 0.35 V
bias)
+0.2/–0.3
+1/–1
LSB
DNL
Differential nonlinearity
3.3 V, CLK =
500 kHz
Generic (1.25 + 0 V
bias)
+0.3/–0.5
+1/–1
LSB
PSRR
Power supply ripple rejection
ratio of DAC output (full scale)
f = dc to 100 kHz, See Note 1
40
42
dB
CLK = 205
MHz –1dB
1 MHz sine wave, offset
bias off
49
MHz, –1 dB
sine wave
applied to
1 MHz sine wave, offset
bias on
42
XTALK
Crosstalk between channels
a
lied to
active
channel,
offset bias
10 MHz sine wave,
offset bias off
49
dB
XTALK
Crosstalk between channels
offset bias
applied to all
channels
10 MHz sine wave,
offset bias on
42
dB
channels
when turned
on, 37.5
ld
ll
30 MHz sine wave,
offset bias off
48
load on all
channels
30 MHz sine wave,
offset bias on
40.5
KIMBAL
Imbalance between DACs
CLK = 80 MHz See Note 3
±2%
V
DAC output compliance
RL = 37.5 ,
Video mode (bias offset
can be added)
0.7
0.72
V
VOC
DAC out ut com liance
voltage (video only)
RL = 37.5 ,
See Note 4
Generic mode (bias
offset cannot be added)
1.25
1.3
V
Co
DAC output capacitance (pin
capacitance)
5
pF
tri
DAC output current rise time
10 to 90% of full-scale, CLK = 80 MHz
3.5
4.2
ns
tfi
DAC output current fall time
10 to 90% of full-scale, CLK = 80 MHz
3.5
4.2
ns
td
Analog output delay
Measured from falling edge of CLKIN to
50% of full-scale transition, See Note 5
6.5
ns
tsa
Analog output settling time
Measured from 50% of full scale
transition on output to output settling,
within 2%, See Note 6
6.6
ns
SFDR
Spurious-free dynamic range
1 MHz, –1 dB FS digital sine input
–55
dB
SFDR
Spurious-free dynamic range
10 MHz, –1 dB FS digital sine input
–43
dB
BW
Bandwidth (3 dB)
90
MHz
Eglitch
Glitch energy
Full-scale code transition at 205 MSPS
25
pVs
NOTES:
1. PSRR is defined as 20*log (ripple voltage at DAC output/ripple voltage at AVDD input). Limits from characterization only.
2. Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limit from characterization only.
3. The imbalance between DACs applies to all possible pairs of the three DACs.
4. Nominal values at RFS = RFS(nom), see figure in Section 7.7. Limit from characterization only. Excludes bias offset.
5. This value excludes the digital process delay, tD(D). Limit from characterization only. Data is clocked in on the rising edge of CLKIN.
Analog outputs become available on the falling edge of CLKIN.
6. Limit from characterization only.
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