參數(shù)資料
型號： THS8200PFPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： GREEN, PLASTIC, HTQFP-80
文件頁數(shù)： 62/101頁
文件大小： 806K
代理商： THS8200PFPG4
5–6
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
SUB-
ADDRESS
R/W
REGISTER
NAME
dtg2_line_
cnt_msb
R
0x7f
dtg2_ip_fmt
Reserved
dtg2_line_cnt(10:8)
dtg2_line_
cnt_lsb
R
0x80
dtg2_line_cnt(7:0)
0x81
Reserved
dtg2_cntl
R/W
0x82
dtg2_fid_
de_cntl
dtg2_rgb_
mode_on
dtg2_em-
bedded_
timing
dtg2_
vsout_pol
dtg2_h
sout_pol
dtg2_fid_
pol
dtg2_vs_
pol
dtg2_hs_
pol
CGMS CONTROL
cgms_cntl_
header
R/W
0x83
Reserved
cgms_en
cgms_header(5:0)
cgms_pay-
load_msb
R/W
0x84
Reserved
cgms_payload(13:8)
cgms_pay-
load_lsb
R/W
0x85
cgms_payload(7:0)
misc_ppl_
lsb
R
0x86
misc_ppl(7:0)
misc_ppl_
lsb
R
0x87
misc_ppl(15:8)
misc_lpf_
lsb
R
0x88
misc_lpf(7:0)
misc_lpf_
msb
R
0x89
misc_lpf(15:8)
5.1
Register Descriptions
Legend: Between { } are shown the name(s), subaddress(es) and bit position(s) where each register can be found in
the register map.
The default register value is shown between [ ] in binary format, and hexadecimal (h) and/or decimal (d) notation
where listed.
5.1.1
System Control (Sub-Addresses 0x02–0x03)
ver(7:0):
Device version
{version 0x02(7..0)}
[0000 0000]
The user can read this register to find out which version of THS8200 is in the system.
vesa_clk:
Clock mode selection
{chip_ctl 0x03(7)}
[0]
0 : Normal operation
1 : All clocks become identical, except for the half-rate clock, and the DLL is bypassed. This is used in VESA mode to
support a direct 205-MHz input clock. No internal 2
× interpolation is available. This mode should be used for all
formats that require a >80 MSPS pixel clock because the internal DLL for 2
× clock generation is specified only up to
80 MSPS.
The half-rate clock is still internally generated if needed to allow, e.g., 148-MHz 20-bit input (1080P).
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