5–11
data_fsadj:
Full-scale adjust control
{data_cntl 0x1C(6)}
[0]
Selects which full-scale setting to use. See FSADJ<n> terminal description for nominal full-scale adjust resistor
values.
0 : Use full-scale setting from resistor connected to FSADJ2 terminal
1 : Use full-scale setting from resistor connected to FSADJ1 terminal
data_ifir12_bypass:
Bypass control 4:2:2 to 4:4:4
{data_cntl 0x1C(5)}
[0]
0 : Interpolation filters before the CSC are in the data path, enabling 4:2:2 to 4:4:4 conversion internally. This mode
should be used when the input data is in 4:2:2 format
1 : Interpolation filters before the CSC are bypassed. This mode should be used when the input data is in 4:4:4
format.
data_ifir35_bypass:
Bypass control 2
interpolation
{data_cntl 0x1C(4)}
[0]
0 : interpolation filters after the CSC are in the data path; enabling 1
× to 2× interpolation of the video data.
1 : interpolation filters after the CSC are bypassed. This mode should be used when 1
× DAC operation is desired.
data_tristate656:
ITU-R.BT656 output bus
{data_cntl 0x1C(3)}
[0]
0 : the ITU-R.BT656 output bus is active.
1 : the ITU-R.BT656 output bus is in the high-impedance state.
data_dman_cntl(2:0):
Data manager control
{data_cntl 0x1C(2:0)}
[011]
Selects the format for the input data manager, as follows:
dman_cntl
MODE
000
30-bit YCbCr/RGB 4:4:4
001
16-bit RGB 4:4:4
010
15-bit RGB 4:4:4
011
20-bit YCbCr 4:2:2
100
10-bit YCbCr 4:2:2 (ITU mode)
Others
(Reserved)
5.1.5
Display Timing Generator Control, Part 1 (Sub-Addresses 0x1D–0x3C)
dtg1_y_blank(9:0):
Y channel blanking level amplitude control
{dtg1_y_sync_msb 0x23(5:4) and dtg1_y_sync1_lsb 0x1D(7:0)}
[10 0000 0000]
Sets the amplitude of the blanking level for the Y channel.
dtg1_y_sync_low(9:0):
Y channel low sync level amplitude control
{dtg1_y_sync_msb 0x23(3:2) and dtg1_y_sync2_lsb 0x1E(7:0)}
[00 0000 0000]
Sets the amplitude of the negative sync and equalization/serration/broad pulses for the Y channel.