參數(shù)資料
型號： THS8200PFPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： GREEN, PLASTIC, HTQFP-80
文件頁數(shù)： 87/101頁
文件大小： 806K
代理商： THS8200PFPG4
7–3
7.3.2
Digital Inputs—DC Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level input current
1
IIL
Low-level input current
VDD_IO = 3.3 V,
Digital inputs and CLK at 0 V for IIL;
–1
A
IIL(CLK)
Low-level input current, CLK
Digital inputs and CLK at 0 V for IIL;
Digital inputs and CLK at 3.6 V for IIH
1
A
IIH(CLK)
High-level input current, CLK
Digital in uts and CLK at 3.6 V for IIH
–1
CI
Input capacitance
TA = 25°C
5
pF
ts
Data and control inputs setup time
1.5
ns
tH
Data and control inputs hold time
0.5
ns
10-bit/20-bit 4:2:2 with CSM, CSC, and 2
interpolation active
73(2)
td(D)
Digital process delay(1)
30-bit 4:4:4
33(2)
pixels
td(D)
Digital rocess delay()
VESA clock mode (DLL, CSM, CSC, FIRs
bypassed)
9
ixels
NOTES:
1. Defined as the delay on Y pixel data, starting from the rising edge of CLKIN, until the clock period when corresponding analog output
becomes available. Because analog output starts to become available on falling edge of CLKIN, an additional 1/2 cycle is to be added
to this delay.
2. CSC contribution, 8 pixels; CSM contribution, 1 pixel; 2
interpolation filter contribution, 18 pixels
相關(guān)PDF資料
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