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參數(shù)資料
| 型號： | THS8200PFPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | GREEN, PLASTIC, HTQFP-80 |
| 文件頁數(shù)： | 82/101頁 |
| 文件大?。?/td> | 806K |
| 代理商： | THS8200PFPG4 |
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6–1
6 Application Information
6.1
Video vs Computer Graphics Application
THS8200 is a highly integrated and flexible universal analog component video/graphics generator that can be used
in any application requiring D/A conversion of video/graphics signals.
In a typical video application (e.g., DVD player, set-top box), the THS8200 receives its input from an MPEG decoder
or media processor engine and converts the signal into the analog domain, thereby generating the correct
timing/frame format for the selected format.
Its ITU-R.BT656 output port could be used to connect to an NTSC/PAL video encoder, such as the Texas Instruments
TVP6000, for regular composite/S-video output.
Note that because the DAC speed is rated up to 205 MSPS, all popular SDTV and HDTV formats, including 1080I
and 720P, are supported in both 1
× and 2× interpolated modes. The 1080P is supported at the 1× rate.
Signal Receiver
(From Satellite,
Cable, DVD Disk)
G/Pb
MPEG Decoder
or
Media
Processor
CCIR656
THS8200
HDTV
Monitor
B/Pr
R/Y
NTSC/PAL
Video Encoder
SDTV
(NTSC/PAL)
Figure 6–1. Typical Video Application
Because of its programmable Hsync/Vsync outputs, the on-chip support for RGB as well as YCbCr color spaces and
its internal color space conversion circuit, and the DAC operational speed of 205 MSPS, all PC graphics formats are
supported as well, up to UXGA at 75 Hz. Video interpolation is now bypassed so that the full 205 MSPS can be used
for the 1
× pixel clock.
3-D/2-D
Graphics
Controller
G
THS8200
VESA
Compatible
CRT Monitor
B
R
24 Bits
HS_OUT
VS_OUT
Figure 6–2. Computer Graphics Application
6.2
DVI to Analog YPbPr/RGB Application
Together with a DVI receiver, this device forms a two-chip solution to convert video or graphics formats sent over a
DVI interface to an analog RGB or YPbPr format using embedded composite sync or separate Hsync, Vsync.
THS8200 connects gluelessly to a DVI receiver using its data input bus and HS_IN and VS_IN terminals. TI DVI 1.0
(with HDCP) receivers provide a data enable (DE) signal that is high during the active video window. The THS8200
can be configured to interpret this DE signal on its FID terminal to automatically insert a user-programmable
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