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Electrical Specifications
122
July 2002 Revised March 2004
SPRS200E
3.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage (except PCI)
DVDD = MIN,
IOH = MAX
2.4
V
VOHP High-level output voltage (PCI)
IOHP = 0.5 mA,
DVDD = 3.3 V
0.9DVDD
V
VOL
Low-level output voltage (except PCI)
DVDD = MIN,
IOL = MAX
0.4
V
VOLP
Low-level output voltage (PCI)
IOLP = 1.5 mA,
DVDD = 3.3 V
0.1DVDD
V
VI = VSS to DVDD no opposing internal
resistor
±10
uA
II
Input current (except PCI)
VI = VSS to DVDD opposing internal
pullup resistor
50
100
150
uA
VI = VSS to DVDD opposing internal
pulldown resistor
150
100
50
uA
IIP
Input leakage current (PCI)§
0 < VIP < DVDD = 3.3 V
±10
uA
EMIF, CLKOUT4, CLKOUT6, EMUx
16
mA
IOH
High-level output current
Video Ports, Timer, TDO, GPIO
(Excluding GP0[15:9, 2, 1]), McBSP
8
mA
PCI/HPI
0.5
mA
EMIF, CLKOUT4, CLKOUT6, EMUx
16
mA
IOL
Low-level output current
Video Ports, Timer, TDO, GPIO
(Excluding GP0[15:9, 2, 1]), McBSP
8
mA
IOL
Low-level output current
SCL0 and SDA0
3
mA
PCI/HPI
1.5
mA
IOZ
Off-state output current
VO = DVDD or 0 V
±10
uA
ICDD
Core supply current#
CVDD = 1.4 V, CPU clock = 600 MHz
793
mA
ICDD
Core supply current#
CVDD = 1.2 V, CPU clock = 500 MHz
555
mA
IDDD
I/O supply current#
DVDD = 3.3 V, CPU clock = 600 MHz
165
mA
IDDD
I/O supply current#
DVDD = 3.3 V, CPU clock = 500 MHz
135
mA
Ci
Input capacitance
10
pF
Co
Output capacitance
10
pF
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
§ PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4,
respectively.
# Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for -600 speed (100-MHz EMIF for
-500 speed). This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing
low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power Consumption
Summary application report (literature number SPRA962).
3.4
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
ADV
ANCE
INFORMA
TION