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參數(shù)資料
| 型號： | TSB12LV26-EP |
| 英文描述： | 672-pin FineLine BGA |
| 中文描述： | 軍事增強(qiáng)塑料的OHCI -山貓基于PCI的1394主控制器 |
| 文件頁數(shù)： | 21/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV26-EP |
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2
–
5
BIT
NUMBER
DESCRIPTION
DIR
FUNCTION
BIT NAME
24
–
25
CHNLCNT
Channel
Count
R/W
Channel count. This field is valid only in isochronous
transmit. This field allows the node to transmit multiple
packets during a single isochronous period. Each packet
must have a different channel number, however,
hardware does not check this. When the isochronous
transmit header is supplied by the DM interface or
automatically inserted by the hardware, a maximum of
four different channels may be accessed in one
isochronous period. In isochronous transmit with
automatic header insert, Header0
–
Header3 CFRs are
used as the isochronous header registers.
26
DMEN
DM Enable
R/W
DMEN controls the transmission of packets from the DM
port. If this bit is 0, transmission through from the DM port
is inhibited. This is used for asynchronous flow control. In
normal operation, if an asynchronous packet trans-
mitted from the DM port receives an acknowledge from
the receiving node other than
ack complete
, this bit will
be set to 0 and DMERROR is asserted high. Software will
need to set this bit to allow further transmission of
asynchronous packets from the DM port. The default and
power-up value is 0.
27
DMHDR
DM Header
Insert Control
R/W
DM header insert bit. When set to 0, the hardware will
automatically insert the header(s) into the DM transmit
data. In receive, setting this bit to 0 will strip off the
header(s) before routing packet to the DM. Header(s) are
always written to the CFR header registers regardless of
the value of DMHDR.
Receive packet routing control encoded bits. These bits
in conjunction with DMASYNC and DMRX bits in the DM
control register controls the routing of the received
packet to either the data mover port or to the GRF. Refer
to Table 4
–
1.
28
–
29
AR0, AR1
Receive
Control
Routing
R/W
30
DMASYNC
DM
Asynchronous
R/W
If this bit is set to 1 the DM port is configured for
asynchronous traffic only. The DM port can not accept
both asynchronous and isochronous traffic. It must be
configured for asynchronous (DMASYNC = 1) or
isochronous (DMASYNC = 0).
31
DMRX
DM Receive
R/W
If this bit is set to 1 the DM port is configured to receive.
The DM port cannot both transmit and receive data at the
same time, it must be configured for either transmit or
receive.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV26IPZT | 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV26IPZTEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP OHCI-LYNX PCI-BASED IEEE 1394 HOST CONTROLLER - Rail/Tube |
| TSB12LV26PZ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZT | 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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