參數(shù)資料
型號(hào)： TSB12LV26-EP
英文描述： 672-pin FineLine BGA
中文描述： 軍事增強(qiáng)塑料的OHCI -山貓基于PCI的1394主控制器
文件頁(yè)數(shù)： 57/106頁(yè)
文件大?。?/td> 605K
代理商： TSB12LV26-EP
5
–
1
5 Data Mover Port Interface
The data mover (DM) port in the TSB12LV32 is the physical medium by which autonomous streams of
different types are piped to/from an application that uses the TSB12LV32. The DM port is meant to handle
an external memory interface of large data packets.
The DM port can support three types of packets:
Asynchronous
Isochronous
Asynchronous Streaming (1394a supported format)
The port can be configured to either transmit or receive data packets at one time (half duplex). A typical
system diagram is shown in Figure 5
–
1:
Application
Phy
Stream Process
(External Memory Interface)
TSB12LV32
μ
Processor/
μ
Controller
(ColdFire
)
Data Mover I/F
Microcontroller Interface
Phy/Link I/F
Figure 5
–
1. A Typical System Diagram
The DM port will perform all operations synchronously, utilizing a 24.576 MHz output clock called DMCLK.
DMCLK is essentially SCLK/2. There is no asynchronous logic within the DM block. All data transfers are
synchronized to the DMCLK output. The DM operates by setting the DM control register at 04h and the
control register at 08h of the CFR. The DM interfaces internally with the configuration register (CFR) block
and the link core (Link) block and interfaces externally with the data mover external interface.
The advantages of the DM port can be summarized as follows:
Transmits or receives large blocks of data at speeds up to 400 Mbits/s.
Allows for a large external FIFO specific to an individual application.
Handles asynchronous, isochronous, or asynchronous streaming packets.
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