參數(shù)資料
型號: TSB12LV26-EP
英文描述: 672-pin FineLine BGA
中文描述: 軍事增強塑料的OHCI -山貓基于PCI的1394主控制器
文件頁數(shù): 37/106頁
文件大小: 605K
代理商: TSB12LV26-EP
2
21
BIT
NUMBER
BIT NAME
FUNCTION
NAME
DIR
DESCRIPTION
30
LPS_RESET
LPS Reset
R/W
Link power status reset. This bit is
set by software and is reset by
hardware. When this bit is set,
hardware will deactivate LPS for a
fixed period to ensure that the Phy
has reset the interface. It will then
reactivate LPS. When this bit is
cleared by hardware, a PHRST
interrupt will also be generated.
31
LPS_OFF
LPS Off
R/W
Link power status off. If set to 1, this
bit will turn off the LPS pulsed
output to the Phy. This bit can also
be turned off from the Phy. Upon
detection of the LINKON pulsed
input signal, this bit will be turned off
allowing LPS to be driven to the
Phy which will, in turn, activate
SCLK and power up the link.
2.2.18
Asynchronous Retry Register at 4Ch
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
ASYNC RETRY COUNT
RETRY INTERVAL
2.2.19
The power-up reset value of this register =
0000_0000
h
.
Asynchronous Retry Register at 4Ch
BIT
NUMBER
BIT NAME
FUNCTION
NAME
DIR
DESCRIPTION
0
7
ASYNC RETRY
COUNT
Retry count
R/W
Asynchronous retry count, specifies the number of times to
automatically retry sending asynchronous packets from the
ATF before giving up. After the retry count is exhausted
FIFOACK interrupt will be generated and the ATACK field in
CFR 30h will be updated to reflect the timeout.
8
15
RETRY
INTERVAL
Retry
interval
R/W
Asynchronous retry interval, is the time in increments of
isochronous cycles, between asynchronous retries.
16
31
RESERVED
RESERVED
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