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參數(shù)資料
| 型號(hào)： | TSB12LV26-EP |
| 英文描述： | 672-pin FineLine BGA |
| 中文描述： | 軍事增強(qiáng)塑料的OHCI -山貓基于PCI的1394主控制器 |
| 文件頁數(shù)： | 97/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26-EP |
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8
–
4
Table 8
–
6. Bus Request Speed Encoding
LR4
–
LR6
DATA RATE
000
S100
010
S200
100
S400
All Others
Invalid
NOTE:
The TSB41LV03A will accept a bus request with an invalid speed code and process
the bus request normally. However, during packet transmission for such a request,
the TSB41LV03A will ignore any data presented by the TSB12LV32 and will
transmit a null packet.
For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 8
–
7.
Table 8
–
7. Read Register Request
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Indicates the beginning of the transfer (always 1).
1
–
3
Request Type
A 100 indicating this is a read register request.
4
–
7
Address
Identifies the address of the Phy register to be read.
8
Stop Bit
Indicates the end of the transfer (always 0).
For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 8
–
8.
Table 8
–
8. Write Register Request
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Indicates the beginning of the transfer (always 1).
1
–
3
Request Type
A 101 indicating this is a write register request.
4
–
7
Address
Identifies the address of the Phy register to be written to.
8
–
15
Data
Gives the data that is to be written to the specified register address.
16
Stop Bit
Indicates the end of the transfer (always 0).
For an acceleration control request the length of the LREQ bit stream is 6 bits as shown in Table 8
–
9.
Table 8
–
9. Acceleration Control Request
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Indicates the beginning of the transfer (always 1).
1
–
3
Request Type
A 110 indicating this is a acceleration control request.
4
Control
Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0.
5
Stop Bit
Indicates the end of the transfer (always 0).
For fair or priority access, the TSB12LV32 sends the bus request (FairReq or PriReq) at least one clock after
the Phy-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (
’
b10) by the Phy,
then any pending fair or priority request is lost (cleared). Additionally, the Phy ignores any fair or priority
requests if the receive state is asserted while the TSB12LV32 is sending the request. The TSB12LV32 may
then reissue the request one clock after the next interface idle.
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving
or transmitting a cycle start message, the TSB12LV32 can issue an isochronous bus request (IsoReq). The
Phy will clear an isochronous request only when the serial bus has been won.
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