參數(shù)資料
型號(hào)： TSB12LV26-EP
英文描述： 672-pin FineLine BGA
中文描述： 軍事增強(qiáng)塑料的OHCI -山貓基于PCI的1394主控制器
文件頁(yè)數(shù)： 22/106頁(yè)
文件大?。?/td> 605K
代理商： TSB12LV26-EP
2
–
6
2.2.3
Control Register at 08h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
R
R
C
C
F
R
F
P
B
T
R
E
E
B
B
B
D
F
C
C
C
C
SIDERCODE
C
I
I
E
The control register dictates the basic operation of the TSB12LV32. The power-up reset value of this register
equals
E004_0200
’
h
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
FLSHERR
Flush GRF
on error
R/W
This bit controls the flushing of the GRF when a packet with
a data CRC error is detected. The power
–
up value is 1,
which means flush the GRF when a data CRC error is
detected.
1
RXSID
Received
Self-ID
packets
R/W
If set, the self-identification (SID) packets generated by Phy
devices during the bus initialization are received and placed
into the GRF as a single packet. The default setting of this
bit is 1. When set to 0, the SIDs are not placed into the GRF.
2
FULLSID
Save full
Self-ID Packet
in GRF
R/W
Save the full self-ID packets.When this bit is 1 the self-ID
data quadlet and its inverse quadlet are saved in the GRF.
When this bit is 0 only the self-ID data quadlet is saved in the
GRF.
3
PHY_PKT_ENA
Phy Packets
Receive
Enable
R/W
Phy packet enable allows reception of all Phy packets. If this
bit is reset to 0, all Phy packets, except for self-IDs, will be
rejected and interrupt HDERR (if not masked) will be
generated. One HDERR interrupt will be generated for
every Phy packet received.
4
BSYCTRL
Busy Control
R/W
BSYCTRL controls which busy status the chip returns to
incoming packets. When this bit is 0 the chip follows normal
busy/retry protocol, only send busy when necessary. When
this bit is 1 the chip sends a busy acknowledge to all
incoming packets following the normal busy/retry protocol.
5
TXEN
Transmit
Enable
R/W
When TXEN is cleared, the transmitter does not arbitrate or
send packets. TXEN bit is cleared following a bus reset, and
all traffic through the DM port will be interrupted. TXEN must
be set before packet transmit can resume. Power-on reset
value of TXEN is 0
6
RXEN
Receive
Enable
R/W
When RXEN is cleared, the receiver does not receive any
packets. This bit is not affected by a bus reset and is set to 0
after a power-on reset.
7
ENA_ACCEL
Acceleration
Enable
R/W
Enable acceleration. When this bit is set, fly-by acceleration
and accelerated arbitration are enabled. This bit cannot be
set while TXEN and RXEN are set. This bit must only be
used with a 1394a capable Phy.
8
ENA_CONCAT
Concatenation
Enable
R/W
Enable concatenation. When this bit is set it allows the link
to concatenate multiple isochronous or asynchronous
packets. This bit must only be used with a 1394a capable
Phy.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV26IPZT 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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TSB12LV26PZ 制造商:TI 制造商全稱:Texas Instruments 功能描述:OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV26PZT 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV26PZTG4 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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