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參數(shù)資料
| 型號(hào)： | TSB12LV26-EP |
| 英文描述： | 672-pin FineLine BGA |
| 中文描述： | 軍事增強(qiáng)塑料的OHCI -山貓基于PCI的1394主控制器 |
| 文件頁(yè)數(shù)： | 63/106頁(yè) |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV26-EP |
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5
–
7
5.1.3
In all the asynchronous receive modes, the packet header information is always loaded into the header
registers. In quadlet receive mode, the first three header quadlets are loaded into the header0at 38h,
header1at 3Ch, and header2at 40h registers, respectively. The trailer quadlet is loaded into the trailer
register at 48h. In block receive mode, the only additional step performed is loading the fourth header
quadlet received into the header3 register at 44h.
Asynchronous Receive
5.1.3.1
Asynchronous Packet Receive Without Headers and Trailer
Step 1:
Asynchronous packet is received through the receiver logic of the link core
Step 2:
The packet headers are stripped off from the packet and loaded into the header registers:
a)
If in quadlet receive mode, the three header quadlets are loaded into the header0
–
header2 registers.
b)
If in block receive mode, the four header quadlets are loaded into the header0
–
header3 registers.
Step 3:
Packet data (payload only) is routed directly to the DM port without any buffering.
Step 4:
Trailer quadlet is loaded into the trailer register at 48h
CFR REGISTER
Step 1
Data
Mover
Port
Header0 Register at 38h
Trailer Register at 48h
LINK CORE
Transmitter
Receiver
Quadlet#0
Step 4
Packet received
from 1394 bus
through the Phy
Step 3 (packet data)
Header1 Register at 3Ch
Quadlet#1
Header2 Register at 40h
Quadlet#2
Header3 Register at 42h
Quadlet#3
Step 2
Loaded only in
Block Receive
Figure 5
–
9. Asynchronous Receive Without Headers and Trailer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV26IPZT | 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV26IPZTEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP OHCI-LYNX PCI-BASED IEEE 1394 HOST CONTROLLER - Rail/Tube |
| TSB12LV26PZ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZT | 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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