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參數(shù)資料
| 型號： | W6692ACF |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 2/101頁 |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACF |
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W6692A
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Table of Contents-
1. GENERAL DESCRIPTION......................................................................................................................... 6
2. FEATURES................................................................................................................................................. 6
3. PIN CONFIGURATIONS............................................................................................................................. 7
4. PIN DESCRIPTION................................................................................................................................... 10
5. SYSTEM DIAGRAM AND APPLICATIONS ............................................................................................. 14
6. BLOCK DIAGRAM.................................................................................................................................... 15
7. FUNCTIONAL DESCRIPTIONS............................................................................................................... 16
7.1 Main Block Functions......................................................................................................................... 16
7.2 Layer 1 Functions Descriptions.......................................................................................................... 17
7.2.1 S/T Interface Transmitter/Receiver..............................................................................................17
7.2.2 Receiver Clock Recovery And Timing Generation........................................................................21
7.2.3 Layer 1 Activation/Deactivation....................................................................................................21
7.2.3.1 States Descriptions And Command/Indication Codes............................................................................21
7.2.3.2 State Transition Diagrams .........................................................................................................................24
7.2.4 D Channel Access Control...........................................................................................................27
7.2.5 Frame Alignment.........................................................................................................................27
7.2.5.1 FAinfA_1fr....................................................................................................................................................27
7.2.5.2 FAinfB_1fr....................................................................................................................................................28
7.2.5.3 FAinfD_1fr....................................................................................................................................................28
7.2.5.4 FAinfA_kfr....................................................................................................................................................28
7.2.5.5 FAinfB_kfr....................................................................................................................................................28
7.2.5.6 FAinfD_kfr....................................................................................................................................................28
7.2.5.7 Faregain.......................................................................................................................................................28
7.2.6 Multiframe Synchronization..........................................................................................................29
7.2.7 Test Functions............................................................................................................................31
7.3 Serial Interface Bus............................................................................................................................ 32
7.4 B Channel Switching.......................................................................................................................... 32
7.5 PCM Port........................................................................................................................................... 34
7.6 D Channel HDLC Controller............................................................................................................... 34
7.6.1 D Channel Message Transfer Modes ..........................................................................................35
7.6.2 Reception of Frames in D Channel..............................................................................................36
7.6.3 Transmission of Frames in D Channel .........................................................................................37
7.7 B Channel HDLC Controller............................................................................................................... 37
7.7.1 Reception of Frames in B Channel ..............................................................................................38
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