參數(shù)資料
型號(hào): W6692ACF
英文描述: ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC
中文描述: 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料
文件頁數(shù): 44/101頁
文件大?。?/td> 851K
代理商: W6692ACF
W6692A
- 44 -
Word 6 (Bytes 12,13) is for Address Register Control, its format is:
15
14
13
12
0
MEN
IEN
PRE
not used
The Address Register Control determines the PCI address register's implementation. Bit 13 is the
prefetchable bit in Memory Base Address register.
MEN
IEN
PCI Configuration Space
Location 10H
Memory Base Address Reg. IO Base Address Reg.
Memory Base Address Reg. Not Implemented
IO Base Address Reg.
Not Implemented
EEPROM empty Memory Base Address Reg. IO Base Address Reg.
PCI Configuration Space
Location 14H
Bit 13
used
yes
yes
no
no
PRE = 0
1
1
0
0
1
0
1
0
Not Implemented
Not Implemented
In all cases, Memory Base Address register allocates 4096 byte spaces and IO Base Address register
allocates 256 byte space.
Word 7 is Power Management Capability register. It replaces the chip's default value if EEPROM is
not empty.
W6692A provides an EPCTL register for on-board access of the serial EEPROM. Software is
responsible for creation of the serial EEPROM’s waveform and timing and can read, write or erase
the EEPROM's content.
7.9.2 8-bit Microprocessor Interface
At power up, the reset pin RST# must be asserted to initialize the chip. At rising edge of RST#, data
value at CLK pin determines the operation modes: active clock for PCI mode, HIGH for Intel bus
mode, LOW for Motorola bus mode.
7.10 Peripheral Control
In PCI card with POTS application, the peripheral devices such as CODEC, DTMF and SLIC can be
directly controlled by W6692A, therefore eliminates the need for another PCI controller chip. The
peripheral control function includes timer, interrupt inputs and programmable IOs or microprocessor
interface.
There are two timers implemented in W6692A: TIMR1 and TIMR2. TIMR1 is a long period timer
whcich can be used to control the cadence of ring tone. TIMR2 is a short period timer which can be
used to generate the 20 Hz ring signal.
TIMR1
TIMR2
Address
10H
4CH
Interrupt status Interrupt mask
DEXIR:T1EXP
DEXIR:TIN2
Output pin
No
TOUT2
Period
(0..127) x 100 mS yes (CNT = 7)
(1..63) mS
Cyclic
DEXIM: T1EXP
DEXIM: TIN2
yes (TMD = 1)
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