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參數(shù)資料
| 型號： | W6692ACF |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 64/101頁 |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACF |
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W6692A
- 64 -
GRLP GCI Mode Remote Loop-back
Setting this bit to 1 activates the remote loop-back function. The 2B+D channels data received from
the GCI bus (DD) interface are looped to the transmitted channels (DU). Valid in GCI slave mode.
SPU
PD Power Down
Software Power Up
SPU
0
PD
1
Description
After U transceiver power down, W6692A will receive the indication DC (Deactivation
Confirmation) from GCI bus and then software has to set SPU
→
0, PD
→
1 to
acknowledge U transceiver, by pulling DU pin to HIGH. W6692A remains normal
operation.
Setting SPU
→
1, PD
→
0 will pull the GCI bus DU line to low. This will enforce
connected layer 1 devices (U transceiver) to deliver GCI bus clocking.
After reception of the indication PU (Power Up indication) the reaction of the
microprocessor should be:
- To write an AR (Activate Request command) as C/I command code in the CIX register.
- To reset the SPU bit and wait for the following ICC (indication code change) interrupt.
Unused.
1
0
0
0
1
1
GMODE GCI Mode
0: Layer 1 is S/T interface; GCI is in master mode. This is default setting.
1: Layer 1 is U interface; GCI is in slave mode.
8.1.33 Peripheral Address Register XADDR Read/Write Address F4H/3DH
Value after reset: Undefined
The register content depends on PCTL:XMODE setting.
XMODE = 0 : Simple IO mode, Valid in PCI or Intel/Motorola Bus mode
7
6
5
4
3
2
1
0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
IO1-0 Read or Write Data of Pins IO1-0
On read operation, these are the present values of pins IO1-0.
On write operation, the data are driven to pins IO1-0 only if PCTL:OE0 = 1.
IO3-2 Read or Write Data of Pins IO3-2
On read operation, these are the present values of pins IO3-2.
On write operation, the data are driven to pins IO3-2 only if PCTL:OE1 = 1.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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