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W6692A
Publication Release Date: July 2000
- 71 -
Revision A1
TABLE 8.4 REGISTER SUMMARY: B1 CHANNEL HDLC
Offset
R/W
Name
7
6
5
4
3
2
1
0
80/20 R
84/21 W
88/22 R/W
B1_RFIFO
B1_XFIFO
B1_CMDR
RACK
RRST
RACT
XACTB
B1_128K
XMS
XME
XRST
8C/23 R/W
90/24 R_clr B1_EXIR
94/25 R/W
B1_MODE
MMS
ITF
RMR
RMR
EPCM
RME
RME
B1_SW1 B1_SW0
RDOV
RDOV
SW56 FTS1
FTS0
XDUN
XDUN
XFR
XFR
B1_EXIM
98/26 R
9C/27 R/W
A0/28 R/W
B1_STAR
B1_ADM1
B1_ADM2
MA17
MA27
RDOV
MA16
MA26
CRCE
MA15
MA25
RMB
MA14
MA24
MA13
MA23
XDOW
MA12
MA22
XBZ
MA10
MA20
MA11
MA21
A4/29 R/W
A8/2A R/W
AC/2B R
B1_ADR1
B1_ADR2
B1_RBCL
RA17
RA27
RBC7
RA16
RA26
RBC6
RA15
RA25
RBC5
RA14
RA24
RBC4
RA13
RA23
RBC3
RA12
RA22
RBC2
RA11
RA21
RBC1
RA10
RA20
RBC0
B0/2C R
B4/2D R/W
B1_RBCH
B1_IDLE
IDLE7
IDLE6
LOV
IDLE5
RBC12
IDLE4
RBC11
IDLE3
RBC10 RBC9
IDLE2 IDLE1 IDLE0
RBC8
8.2.1 B1_ch receive FIFO
B1_RFIFO
Read Address 80H/20H
The B1_RFIFO is a 128-byte depth FIFO memory with programmable threshold. The threshold value
determines when to generate an interrupt.
When more than a threshold length of data has been received, a RMR interrupt is generated. After an
RMR interrupt, 64 or 96 bytes can be read out, depending on the threshold setting.
In transparent mode, when the end of frame has been received, a RME interrupt is generated. After
an RME interrupt, the number of bytes available is less than or equal to the threshold value.
8.2.2 B1_ch transmit FIFO
B1_XFIFO
Write Address 84H/21H
The B1_XFIFO is a 128-byte depth FIFO with programmable threshold value. The threshold setting is
the same as B1_RFIFO.
When the number of empty locations is equal to or greater than the threshold value, a XFR interrupt
is generated. After a XFR interrupt, up to 64 or 96 bytes of data can be written into this FIFO for
transmission.