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參數(shù)資料
| 型號(hào)： | W6692ACF |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁(yè)數(shù)： | 78/101頁(yè) |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACF |
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W6692A
- 78 -
RBC12-8 Receive Byte Count
Used in transparent mode only. Five most significant bits of the total number of bytes are in a
received frame. These bits are valid only after a RME interrupt and remain valid until the frame is
acknowledge via the RACK bit.
Note
: The frame length equals RBC12-0. This length is between 1 and 8191. After a RME interrupt, the number of data available in
B1_RFIFO is frame length modulus threshold.
Remainder = RBC12-0 MOD threshold
No of available data = remainder
No of available data = threshold
The remainder equals RBC5-0 if threshold is 64.
if remainder
≠
0 or
if remainder = 0
8.2.14 B1_ch Transmit Idle Pattern
B1_IDLE
Read/Write
Address B4H/2DH
Value after reset: FFH
7
6
5
4
3
2
1
0
IDLE7
IDLE6
IDLE5
IDLE4
IDLE3
IDLE2
IDLE1
IDLE0
IDLE7-0
This pattern is transmitted when the transmitter is active and transmit FIFO is empty. Valid in
extended transparent mode only.
8.3 B2 HDLC Controller
TABLE 8.5 REGISTER ADDRESS MAP: B2 CHANNEL HDLC
Offset
C0/30
C4/31
C8/32
CC/33
D0/34
D4/35
D8/36
DC/37
E0/38
E4/39
E8/3A
EC/3B
F0/3C
B8/2E
Access
R
W
R/W
R/W
R_clear B2_EXIR
R/W
B2_EXIM
R
B2_STAR
R/W
B2_ADM1
R/W
B2_ADM2
R/W
B2_ADR1
R/W
B2_ADR2
R
B2_RBCL
R
B2_RBCH
R/W
B2_IDLE
Register Name
B2_RFIFO
B2_XFIFO
B2_CMDR
B2_MODE
Description
B2 channel receive FIFO
B2 channel transmit FIFO
B2 channel command register
B2 channel mode control
B2 channel extended interrupt
B2 channel extended interrupt mask
B2 channel status register
B2 channel address mask 1
B2 channel address mask 2
B2 channel address 1
B2 channel address 2
B2 channel receive frame byte count low
B2 channel receive frame byte count high
B2 channel transmit idle pattern
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