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參數(shù)資料
| 型號(hào)： | W6692ACF |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 74/101頁 |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACF |
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W6692A
- 74 -
B1_SW1-0 B Channel Switching Select
These two bits, along with PXC bit in PCTL register, determine the connection in B1 channel. See
section 7.4 for details.
Note
: The connection with micro-controller is through HDLC controller. When HDLC connects with layer 1, either transparent or
extended transparent mode can be used. When HDLC connects with PCM port/GCI bus, only extended transparent mode can be
used and the EPCM bit must be set to enable PCM function.
SW56 Switch 56 Traffic
0: The data rate in B1 channel is 64 kbps.
1: The data rate in B1 channel is 56 kbps. The most significant bit in each octet is fixed at "1".
Note
: In 56 kbps mode, only transparent mode can be used.
FTS1-0 FIFO Threshold Select
These two bits determine the B1 channel receive and transmit FIFO's threshold setting. An interrupt
is generated when the number of received data or the number of vacancies in XFIFO reaches the
threshold value.
FTS1
0
0
1
1
FTS0
0
1
0
1
Threshold (byte)
64
Reserved
96
Not allowed
8.2.5 B1_ch Extended Interrupt Register
B1_EXIR
Read_clear
Address 90H/24H
Value after reset: 00H
7
6
5
4
3
2
1
0
RMR
RME
RDOV
XFR
XDUN
RMR Receive Message Ready
At least a threshold lenth of data has been stored in the B1_RFIFO.
RME Receive Message End
Used in transparent mode only. The last block of a frame has been received. The frame length can
be found in B1_RBCH + B1_RBCL registers. The number of data available in the B1_RFIFO equals
frame lenth modulus threshold. The result of CRC check is indicated by B1_STAR:CRCE bit.
When the number of last block of a frame equals the threshold, only RME interrupt is generated.
RDOV Receive Data Overflow
Data overflow occurs in the receive FIFO. The incoming data will overwrite the data in the receive
FIFO.
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