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參數(shù)資料
| 型號(hào)： | W6692ACF |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁(yè)數(shù)： | 50/101頁(yè) |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACF |
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W6692A
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8.1.4 D_ch Mode Register
D_MODE
Read/Write
Address 0CH/03H
Value after reset : 00H
7
6
5
4
3
2
1
0
0
RACT XACTB
0
PMES
MFD
DLP
RLP
RACT Receiver Active
Setting this bit activates the D_ch HDLC receiver. This bit can be read. The receiver must be in
active state in order to receive data.
XACTB Transmitter Active
Resetting this bit activates the D_ch HDLC transmitter. This bit can be read. The transmitter must be
in active state in order to transmit data. Note this bit is active LOW.
PMES PME Trigger Select
0: PCI power management event triggered by D_RMR or D_RME interrupt
1: PCI power management event triggered by layer 1enters F7 state
MFD Multiframe Disable
This bit is used to enable or disable the multiframe structure on S/T interface:
0 : Multiframe is enabled
1 : Multiframe is disabled
DLP Digital Loopback
Setting this bit activates the digital loopback function. The transmitted digital 2B+D channels are
looped to the received 2B+D channels. Note that after hardware reset, the internal clocks will turn off
if the S bus is not connected or if there is no signal on the S bus. In this case, the C/I command ECK
must be issued to enable loopback function.
RLP Remote Loopback
Setting this bit to "1" activates the remote loopback function. The received 2B channels from the S
interface are looped to the transmitted 2B channels of S interface. The D channel is not looped in this
loopback function.
Bits 7, 4 Reserved
These bits are reserved. The write values are don't care, but are read as zero.
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