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參數(shù)資料
| 型號： | W6692ACF |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 37/101頁 |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACF |
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W6692A
Publication Release Date: July 2000
- 37 -
Revision A1
7.6.3 Transmission of Frames in D Channel
A 128-byte FIFO is provided in the transmit direction. If the transmit FIFO is ready (which is indicated
by a D_XFR interrupt), the micro-processor can write up to 64 bytes of data into the FIFO and use the
XMS command bit to start frame transmission. The HDLC transmitter sends the opening flag first and
then sends the data in the transmit FIFO.
The microprocessor must write the address, control and information field of a frame into the transmit
FIFO.
Every time no more than 64 bytes of data are left in the transmit FIFO, the transmitter generates a
D_XFR interrupt to request another block of data. The microprocessor can then write further data to
the transmit FIFO and enables the subsequent transmission by issuing an XMS command.
If the data written to the FIFO is the last segment of a frame, the microprocessor issues the XME
(Transmit Message End) and XMS command bits to finish the frame transmission. The transmitter
then transmits the data in the FIFO and appends CRC and closing flag.
If the microprocessor fails to respond the D_XFR interrupt within a given time (32 mS), a data
underrun condition will occur. The W6692A will automatically reset the transmitter and send inter
frame time fill pattern (all 1's) on D channel. The microprocessor is informed about this condition via
an XDUN (Transmit Data Underrun) interrupt in D_EXIR register. The microprocessor must wait until
transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the
data.
It is possible to abort a frame by issuing a D_CMDR:XRST (D channel Transmitter Reset) command.
The XRST command resets the transmitter and causes a transmit FIFO ready condition.
After the microprocessor has issued the XME command, the successful termination of transmission is
indicated by an D_XFR interrupt.
The inter-frame time fill pattern must be all 1's, according to ITU-T I.430.
Collisions which occur on the D channel of S interface will cause an D_EXIR:XCOL interrupt. A XRST
(Transmitter Reset) command must be issued and software must wait until transmit FIFO ready (via
XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
7.7 B Channel HDLC Controller
There are two B channel HDLC controllers. Each B channel HDLC controller provides two operation
modes :
- Transparent mode
Characteristics:
* 2 byte address field
* Receive address comparison maskable bit-by-bit
* Data between opening flag and CRC (not included) stored in receive FIFO
* Flag generation/ deletion
* Frame Check Sequence generation/ check with CRC_ITU-T polynominal
* Zero bit insertion/ deletion
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