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參數(shù)資料
| 型號： | W6692ACF |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 75/101頁 |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACF |
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W6692A
Publication Release Date: July 2000
- 75 -
Revision A1
XFR Transmit FIFO Ready
This interrupt indicates that up to a threshold length of data can be written into the B1_XFIFO.
XDUN Transmit Data Underrun
This interrupt occurs when the B1_XFIFO has run out of data. In this case, the W6692A will
automatically reset the transmitter and send the inter frame time fill pattern on B channel. The
software must wait until transmit FIFO ready condition (via XFR interrupt), re-write data, and issue
XMS command to re-transmit the data.
8.2.6 B1_ch Extended Interrupt Mask Register B1_EXIM Read/Write Address
94H/25H
Value after reset: FFH
7
6
5
4
3
2
1
0
RMR
RME
RDOV
XFR
XDUN
Setting the bit to "1" masks the corresponding interrupt source in B1_EXIR register. Masked interrupt
status bits are read as zero when B1_EXIR register is read. They are internally stored and pending
until the mask bits are zero.
All the interrupts in B1_EXIR will be masked if the IMASK : B1_EXI bit is set to "1".
8.2.7 B1_ch Status Register B1_STAR Read Address 98H/26H
Value after reset: 20H
7
6
5
4
3
2
1
0
RDOV
CRCE
RMB
XDOW
XBZ
RDOV Receive Data Overflow
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive
FIFO. The overflow condition will set both the status and interrupt bits. It is recommended that
software must read the RDOV bit after reading data from receive FIFO at RMR or RME interrupt. The
software must abort the data and issue a RRST command to reset the receiver if RDOV = 1.
CRCE CRC Error
Used in transparent mode only. This bit indicates the result of frame CRC check:
0 : CRC correct
1 : CRC incorrect
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