![](http://datasheet.mmic.net.cn/230000/W6692A_datasheet_15631120/W6692A_3.png)
W6692A
Publication Release Date: July 2000
- 3 -
Revision A1
7.7.2 Transmission of Frames in B Channel..........................................................................................39
7.8 GCI Mode Serial Interface Bus .......................................................................................................... 40
7.8.1 GCI Mode C/I0 Channel Handling
..........................................................................................41
7.8.2 GCI Mode Monitor Channel Handling
....................................................................................41
7.9 PCI/MP Interface Circuit..................................................................................................................... 42
7.9.1 PCI Slave Mode And Configuration Serial EEPROM....................................................................42
7.9.2 8-bit Microprocessor Interface.....................................................................................................44
7.10 Peripheral Control............................................................................................................................ 44
8. REGISTER DESCRIPTIONS.................................................................................................................... 45
8.1 Chip Control and D_ch HDLC Controller............................................................................................ 45
8.1.1 D_ch receive FIFO
8.1.2 D_ch transmit FIFO
8.1.3 D_ch command register
8.1.4 D_ch Mode Register
8.1.5 Timer 1 Register
8.1.6 Interrupt Status Register
ISTA Read_clear Address 14H/05H.........................................51
8.1.7 Interrupt Mask Register
IMASK Read/Write Address 18H/06H..............................................52
8.1.8 D_ch Extended Interrupt Register
D_EXIR Read_clear Address 1CH/07H....................52
8.1.9 D_ch Extended Interrupt Mask Register
D_EXIM Read/Write Address 20H/08H................53
8.1.10 D_ch Status Register D_XSTA Read Address 24H/09H.............................................54
8.1.11 D_ch Receive Status Register D_RSTA Read Address 28H/0AH.............................54
8.1.12 D_ch SAPI Address Mask D_SAM Read/Write Address 2CH/0BH.......................55
8.1.13 D_ch SAPI1 Register
8.1.14 D_ch SAPI2 Register
8.1.15 D_ch TEI Address Mask D_TAM Read/Write Address 38H/0EH..............................55
8.1.16 D_ch TEI1 Register D_TEI1 Read/Write Address 3CH/0FH................................56
8.1.17 D_ch TEI2 Register D_TEI2 Read/Write Address 40H/10H...................................56
8.1.18 D_ch Receive Frame Byte Count High D_RBCH Read Address 44H/11H................56
8.1.19 D_ch Receive Frame Byte Count Low D_RBCL Read Address 48H/12H.................57
8.1.20 Timer 2 TIMR2 Write Address 4CH/13H...........................................................57
8.1.21 Layer 1_Ready Code L1_RC
Read/Write Address 50H/14H.....................................57
8.1.22 Control Register
8.1.23 Command/Indication Receive Register
8.1.24 Command/Indication Transmit Register
8.1.25 S/Q Channel Receive Register SQR Read Address 60H/18H................................59
8.1.26 S/Q Channel Transmit Register SQX
Read
/Write Address 64H/19H .......................60
8.1.27 Peripheral Control Register
8.1.28 Monitor Receive Channel 0 MO0R Read Address 6CH/1BH...............................61
D_RFIFO Read Address 00H/00H .......................................................49
D_XFIFO Write Address 04H/01H.........................................................49
D_CMDR Write Address 08H/02H ..................................................49
D_MODE Read/Write Address 0CH/03H..............................................50
TIMR1 Read/Write Address 10H/04H.....................................................51
D_SAP1 Read/Write Address 30H/0CH...............................55
D_SAP2 Read/Write Address 34H/0DH .................................55
CTL Read/Write Address 54H/15H...........................................................58
CIR Read Address 58H/16H ..............................58
CIX Read/Write Address 5CH/17H.........................59
PCTL Read/Write Address 68H/1AH.............................60