參數(shù)資料
型號: XC3SD1800A-4CSG484LI
廠商: Xilinx Inc
文件頁數(shù): 21/101頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 DSP 484CSGBGA
標準包裝: 84
系列: Spartan®-3A DSP
LAB/CLB數(shù): 4160
邏輯元件/單元數(shù): 37440
RAM 位總計: 1548288
輸入/輸出數(shù): 309
門數(shù): 1800000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-FBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 484-CSPBGA
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
26
Input Timing Adjustments
Table 22: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Units
Speed Grade
-5
-4
Single-Ended Standards
LVTTL
0.62
ns
LVCMOS33
0.54
ns
LVCMOS25
0.00
ns
LVCMOS18
0.83
ns
LVCMOS15
0.60
ns
LVCMOS12
0.31
ns
PCI33_3
0.41
ns
PCI66_3
0.41
ns
HSTL_I
0.72
ns
HSTL_III
0.77
ns
HSTL_I_18
0.69
ns
HSTL_II_18
0.69
ns
HSTL_III_18
0.79
ns
SSTL18_I
0.71
ns
SSTL18_II
0.71
ns
SSTL2_I
0.68
ns
SSTL2_II
0.68
ns
SSTL3_I
0.78
ns
SSTL3_II
0.78
ns
Differential Standards
LVDS_25
0.76
ns
LVDS_33
0.79
ns
BLVDS_25
0.79
ns
MINI_LVDS_25
0.78
ns
MINI_LVDS_33
0.79
ns
LVPECL_25
0.78
ns
LVPECL_33
0.79
ns
RSDS_25
0.79
ns
RSDS_33
0.77
ns
TMDS_33
0.79
ns
PPDS_25
0.79
ns
PPDS_33
0.79
ns
DIFF_HSTL_I_18
0.74
ns
DIFF_HSTL_II_18
0.72
ns
DIFF_HSTL_III_18
1.05
ns
DIFF_HSTL_I
0.72
ns
DIFF_HSTL_III
1.05
ns
DIFF_SSTL18_I
0.71
ns
DIFF_SSTL18_II
0.71
ns
DIFF_SSTL2_I
0.74
ns
DIFF_SSTL2_II
0.75
ns
DIFF_SSTL3_I
1.06
ns
DIFF_SSTL3_II
1.06
ns
Notes:
1.
The numbers in this table are tested using the methodology
presented in Table 26 and are based on the operating conditions
set forth in Table 7, Table 10, and Table 12.
2.
These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
Table 22: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Units
Speed Grade
-5
-4
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