參數資料
| 型號： | XC3SD1800A-4CSG484LI |
| 廠商： | Xilinx Inc |
| 文件頁數： | 30/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 3 DSP 484CSGBGA |
| 標準包裝： | 84 |
| 系列： | Spartan®-3A DSP |
| LAB/CLB數： | 4160 |
| 邏輯元件/單元數： | 37440 |
| RAM 位總計： | 1548288 |
| 輸入/輸出數： | 309 |
| 門數： | 1800000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-FBGA，CSPBGA |
| 供應商設備封裝： | 484-CSPBGA |
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
34
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (VREF, RREF, and VMEAS) correspond directly
not confuse VREF (the termination voltage) from the IBIS
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
Delays for a given application are simulated according to its
specific load conditions as follows:
1.
Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 8.
CREF is zero.
2.
Record the time to VM.
3.
Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including VREF, RREF, CREF,
and VMEAS values) or capacitive value to represent the
load.
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 25) to
yield the worst-case delay of the PCB trace.
Simultaneously Switching Output
Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
guidelines. For each device/package combination, Table 27
provides the number of equivalent VCCO/GND pairs. The
equivalent number of pairs is based on characterization and
may not match the physical number of pairs. For each
output signal standard and drive strength, Table 28
recommends the maximum number of SSOs, switching in
the same direction, allowed per VCCO/GND pair within an
I/O bank. The guidelines in Table 28 are categorized by
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
Multiply the appropriate numbers from Table 27 and
Table 28 to calculate the maximum number of SSOs
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The SSO values assume that the VCCAUX is powered at
3.3V. Setting VCCAUX to 2.5V provides better SSO
characteristics.
Table 27: Equivalent VCCO/GND Pairs per Bank
Device
Package Style (including Pb-free)
CS484
FG676
XC3SD1800A
6
9
XC3SD3400A
6
10
相關PDF資料 |
PDF描述 |
|---|---|
| XC3SD3400A-4FGG676I | SPARTAN-3ADSP FPGA 3400K 676FBGA |
| XC4036XLA-09HQ240C | IC FPGA C 2.5V 288 I/O 240HQFP |
| XC4062XL-09HQ240C | IC FPGA C-TEMP 3.3V 240-HQFP |
| XC4085XL-3BG560I | IC FPGA I-TEMP 3.3V 3SPD 560MBGA |
| XC4VLX100-10FFG1513C | IC FPGA VIRTEX-4 100K 1513-FBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC3SD1800A-4FG676C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3A 1.8M GATES 37440 CELLS 667MHZ 1.2V 676FBGA - Trays 制造商:Xilinx 功能描述:IC FPGA 519 I/O 676FBGA 制造商:Xilinx 功能描述:SPARTAN-3ADSP FPGA 1800K 676FBGA |
| XC3SD1800A-4FG676I | 功能描述:SPARTAN-3ADSP FPGA 1800K 676FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan®-3A DSP 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC3SD1800A-4FGG676C | 功能描述:SPARTAN-3ADSP FPGA 1800K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan®-3A DSP 標準包裝:24 系列:ECP2 LAB/CLB數:1500 邏輯元件/單元數:12000 RAM 位總計:226304 輸入/輸出數:131 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） |
| XC3SD1800A-4FGG676CES | 制造商:Xilinx 功能描述: |
| XC3SD1800A-4FGG676I | 功能描述:SPARTAN-3ADSP FPGA 1800K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan®-3A DSP 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
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