參數(shù)資料
型號: XR16L651
廠商: Exar Corporation
英文描述: 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器(帶32字節(jié)先進先出))
中文描述: 2.5V,3.3V與5V的低功耗的UART與32字節(jié)的FIFO(2.5伏,3.3伏和5V的低功耗通用異步接收器/發(fā)送器(帶32字節(jié)先進先出))
文件頁數(shù): 11/46頁
文件大?。?/td> 516K
代理商: XR16L651
á
XR16L651
2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO
PRELIMINARY
REV. P1.0.0
11
3.0
CRYSTAL OSCILLATOR OR EXTERNAL
CLOCK.
The 651 includes an on-chip oscillator (XTAL1 and
XTAL2). The crystal oscillator provides the system
clock to the Baud Rate Generators (BRG) in the
UART. XTAL1 is the input to the oscillator or external
clock buffer input with XTAL2 pin being the output. For
programming details, see “Programmable Baud Rate
Generator” on page 11 .
The on-chip oscillator is designed to use an industry
standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance
load, ESR of 20-80 ohms and 100ppm frequency tol-
erance) connected externally between the XTAL1 and
XTAL2 pins (see Figure 7). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom
rates. Typically, the oscillator connections are shown
in Figure 7. For further reading on oscillator circuit
please see application note DAN108 on EXAR’s web
site
3.1
P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
The UART has its own Baud Rate Generator (BRG)
with a prescaler for the transmiter. The prescaler is
controlled by a software bit in the MCR register. The
MCR register bit-7 sets the prescaler to divide the in-
put crystal or external clock by 1 or 4. The clock out-
put of the prescaler goes to the BRG. The BRG fur-
ther divides this clock by a programmable divisor be-
tween 1 and (2
16
-1) to obtain a 16X sampling clock
of the serial data rate. The sampling clock is used by
the transmitter for data bit shifting and
receiver for da-
ta sampling. The BRG divisor (DLL and DLM regis-
ters) defaults to a random value upon power up or a
reset . Therefore, the BRG must be programmed dur-
ing initialization to the operating data rate.
Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the
operating data rate. Table 3 shows the standard data
rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. When using a non-standard
data rate crystal or external clock, the divisor value
can be calculated for DLL/DLM with the following
equation.
F
IGURE
7. T
YPICAL
OSCILLATOR
CONNECTIONS
C1
22-47pF
C2
22-47pF
Y1
1.8432 - 24 MHz
R1
0-120
(Optional)
R2
500K - 1M
XTAL1
XTAL2
F
IGURE
8. B
AUD
R
ATE
G
ENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
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