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參數(shù)資料
| 型號： | XR16L651 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）) |
| 中文描述： | 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）） |
| 文件頁數(shù)： | 27/46頁 |
| 文件大?。?/td> | 516K |
| 代理商： | XR16L651 |
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XR16L651
2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO
PRELIMINARY
REV. P1.0.0
27
MCR[1]: RTS# Pins
The RTS# pin is a modem control output and may be
used for automatic hardware flow control by enabled
by EFR bit-6. If the modem interface is not used, this
output may be used for general purpose.
Logic 0 = Force RTS# output to a logic 1. (default)
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: OP1# Output
OP1# is a general purpose output.
Logic 0 = OP1# output is at logic 1.
Logic 1 = OP1# output is at logic 0
MCR[3]: OP2# or IRQn Enable during PC Mode
OP2# is a general purpose output available during
the Intel or Motorola bus interface mode of operation.
In the PC bus mode, it enables the IRQn operation.
See PC Mode section.
During Intel or Motorola Bus Mode Operation:
Logic 0 = OP2# output is at logic 1.
Logic 1 = OP2# output is at logic 0.
During PC Mode Operation:
Logic 0 = Disable IRQn operation. (default).
Logic 1 = Enable IRQn operation.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode. (default)
Logic 1 = Enable local loopback mode, see loop-
back section and Figure 11.
MCR[5]: Active/Tristate Interrupt Output Enable
Logic 0 = Enable active or tristate interrupt output
(default).
Logic 1 = Enable open source interrupt output
mode. See Table 2 for detailed information.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 is the default unless the IR mode is forced by
the ENIR pin. This bit can overwrite the ENIR state af-
ter a power up or reset.
Logic 0 = Enable the standard modem receive and
transmit input/output interface. (Default)
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. The TX/RX output/input are routed
to the infrared encoder/decoder. The data input and
output levels conform to the IrDA infrared interface
requirement. The infrared TX output is at logic 0
during idle condition. The infrared receive data
input polarity is also logic 0, however, it may be
inverted when using an infrared modules that pro-
vides inverted signal output. Use register XFR bit-1
to invert the receive input signal level going to the
infrared decoder. Also see XFR bit-0 for half-duplex
operation where the receiver can be disabled while
transmiting.
MCR[7]: Clock Prescaler Select
Logic 0 = Divide by one. The input clock from the
crystal or external clock is fed directly to the Pro-
grammable Baud Rate Generator without further
modification, i.e., divide by one. (default).
Logic 1 = Divide by four. The prescaler divides the
input clock from the crystal or external clock by four
and feeds it to the Programmable Baud Rate Gen-
erator, hence, data rates become one forth.
6.8
This register provides the status of data transfers be-
tween the UART and the host.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or
FIFO. (default).
Logic 1 = Data has been received and is saved in
the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
Logic 0 = No overrun error. (default)
Logic 1 = Overrun error. A data overrun error condi-
tion occurred in the receive shift register. This hap-
pens when additional data arrives while the FIFO is
full. In this case the previous data in the receive
shift register is overwritten. Note that under this
condition the data byte in the receive shift register
is not transferred into the FIFO, therefore the data
in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Flag
Logic 0 = No parity error. (default)
Logic 1 = Parity error. The receive character in RHR
does not have correct parity information and is sus-
pect. This error is associated with the character
available for reading in RHR.
LSR[3]: Receive Data Framing Error Flag
Logic 0 = No framing error. (default)
Logic 1 = Framing error. The receive character did
not have a valid stop bit(s). This error is associated
with the character available for reading in RHR.
LSR[4]: Receive Break Flag
Logic 0 = No break condition. (default)
Logic 1 = The receiver received a break signal (RX
was a logic 0 for at least one character frame time).
In the FIFO mode, only one break character is
loaded into the FIFO. The break indication remains
L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L651CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V UART WITH 32-BYTE FIFO |
| XR16L651CM-0A-EVB | 功能描述:UART 接口集成電路 Supports L651 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CM-F | 功能描述:UART 接口集成電路 UARTW/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CMTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L651CMTR-F |
| XR16L651IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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