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參數(shù)資料
| 型號(hào)： | XR16L651 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）) |
| 中文描述： | 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）） |
| 文件頁(yè)數(shù)： | 26/46頁(yè) |
| 文件大?。?/td> | 516K |
| 代理商： | XR16L651 |
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XR16L651
2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO
REV. P1.0.0
á
PRELIMINARY
26
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in con-
junction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The
parity bit is a simple way used in communications for
data integrity check. See Table 11 for parity selection
summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the trans-
mission while the receiver checks for parity error of
the data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same for-
mat. (default).
Logic 1 = EVEN Parity is generated by forcing an
even the number of logic 1’s in the transmitted char-
acter. The receiver must be programmed to check
the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced. (default)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity
bit is forced to a logical 1 for the transmit and
receive data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity
bit is forced to a logical 0 for the transmit and
receive data.
LCR[6]: Transmit Break Enable
When enabled the Break control bit it causes a
break condition to be transmitted (the TX output is
forced to a “space’, logic 0, state). This condition
remains until disabled by setting LCR bit-6 to a
logic 0.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a
“space”, logic 0, for alerting the remote receiver of
a line break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected. (default)
Logic 1 = Divisor latch registers are selected.
6.7
M
ODEM
C
ONTROL
R
EGISTER
(MCR)
OR
G
EN
-
ERAL
P
URPOSE
O
UTPUTS
C
ONTROL
.
The MCR register is used for controlling the serial/
modem interface signals or general purpose inputs/
outputs.
MCR[0]: DTR# Pins
The DTR# pin is a modem control output. If the mo-
dem interface is not used, this output may be used for
general purpose.
Logic 0 = Force DTR# output to a logic 1. (default)
Logic 1 = Force DTR# output to a logic 0.
BIT-2
W
ORD
LENGTH
S
TOP
BIT
LENGTH
(B
IT
TIME
(
S
))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
T
ABLE
11: P
ARITY
SELECTION
LCR B
IT
-5 LCR B
IT
-4
LCR B
IT
-
3
P
ARITY
SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark,
“1”
1
1
1
Forced parity to space,
“0”
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| XR16L651CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V UART WITH 32-BYTE FIFO |
| XR16L651CM-0A-EVB | 功能描述:UART 接口集成電路 Supports L651 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CM-F | 功能描述:UART 接口集成電路 UARTW/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CMTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L651CMTR-F |
| XR16L651IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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