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參數(shù)資料
| 型號(hào)： | XR16L651 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）) |
| 中文描述： | 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）） |
| 文件頁數(shù)： | 22/46頁 |
| 文件大小： | 516K |
| 代理商： | XR16L651 |
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XR16L651
2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO
REV. P1.0.0
á
PRELIMINARY
22
6.3
The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR)
register.
6.3.1
IER versus Receive FIFO Interrupt Mode
Operation
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the RHR interrupts (see ISR bits 2 and 3) status will
reflect the following:
I
NTERRUPT
E
NABLE
R
EGISTER
(IER)
A.
The receive data available interrupts are issued
to the host when the FIFO has reached the pro-
grammed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
B.
FIFO level will be reflected in the ISR register
when the FIFO trigger level is reached. Both the
ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger
level.
C.
The receive data ready bit (LSR BIT-0) is set as
soon as a character is transferred from the shift
F
IGURE
14. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Flags in
LSR bits
4:2
F
IGURE
15. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
E
(
E
L
32 bytes by 11-bit
wide FIFO
Receive Data Characters
FIFO Trigger=16
Example:
- RX FIFO trigger level selected at 16 bytes
Data fills to 24
Data falls to 8
Data Bit
Validation
Receive Data
FIFO
(32-byte)
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) is programmed at FIFO
trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L651CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V UART WITH 32-BYTE FIFO |
| XR16L651CM-0A-EVB | 功能描述:UART 接口集成電路 Supports L651 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CM-F | 功能描述:UART 接口集成電路 UARTW/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CMTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L651CMTR-F |
| XR16L651IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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