參數(shù)資料
型號(hào)： XR16L651
廠商： Exar Corporation
英文描述： 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）)
中文描述： 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出））
文件頁(yè)數(shù)： 30/46頁(yè)
文件大?。?/td> 516K
代理商： XR16L651
XR16L651
2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO
REV. P1.0.0
á
PRELIMINARY
30
6.14 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
This register contains the device ID (0x04 for
XR16L651). Prior to reading this register, DLL and
DLM should be set to 0x00.
6.15 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
This register contains the device revision information.
For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
6.16 E
NHANCED
F
EATURE
R
EGISTER
(EFR)
Enhanced features are enabled or disabled using this
register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 12). When the Xon1 and Xon2 and Xoff1 and
Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential characters. Cau-
tion: note that whenever changing the TX or RX flow
control bits, always reset all bits back to logic 0 (dis-
able) before programming a new setting.
EFR BIT 0-3: Software Flow Control Select
Combinations of software flow control can be select-
ed by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER
bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7,
XFR bits 0-7 and IRPW bits 0-7 to be modified. After
modifying any enhanced bits, EFR bit-4 can be set to
a logic 0 to latch the new values. This feature pre-
vents legacy software from altering or overwriting the
enhanced functions once set. Normally, it is recom-
mended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced fea-
tures. IER bits 4-7, ISR bits 4-5, FCR bits 4-5,
MCR bits 5-7, XFR bits 0-7 and IRPW bits 0-7 are
saved to retain the user settings. After a reset, the
IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits
5-7, XFR bits 0-7 and IRPW bits 0-7 are set to a
logic 0 to be compatible with ST16C554 mode.
(default).
Logic 1 = Enables the above-mentioned register
bits to be modified by the user.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled.
(default)
Logic 1 = Special Character Detect Enabled. The
UART compares each incoming receive character
T
ABLE
12: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
EFR
BIT
-3
C
ONT
-3
EFR
BIT
-2
C
ONT
-2
EFR
BIT
-1
C
ONT
-1
EFR
BIT
-0
C
ONT
-0
T
RANSMIT
AND
R
ECEIVE
S
OFTWARE
F
LOW
C
ONTROL
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
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