參數(shù)資料
型號(hào)： XR16L651
廠商： Exar Corporation
英文描述： 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）)
中文描述： 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出））
文件頁(yè)數(shù)： 29/46頁(yè)
文件大?。?/td> 516K
代理商： XR16L651
á
XR16L651
2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO
PRELIMINARY
REV. P1.0.0
29
6.10 M
ODEM
S
TATUS
R
EGISTER
(MSR) - R
EAD
O
NLY
This register provides the current state of the modem
interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register
are used to indicate the changed information. These
bits are set to a logic 1 whenever a signal from the
modem changes state. These bits may be used as
general purpose inputs/outpus when they are not
used with modem signals.
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since
the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since
the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0
to a logic 1, ending of the ringing signal. A modem
status interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed
state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow
control signal input if it is enabled and selected by Au-
to CTS (EFR bit-7). Auto CTS flow control allows
starting and stopping of local data transmissions
based on the modem CTS# signal. A logic 1 on the
CTS# pin will stop UART transmitter as soon as the
current character has finished transmission, and a
logic 0 will resume data transmission. Normally MSR
bit-4 bit is the compliment of the CTS# input. However
in the loopback mode, this bit is equivalent to the
RTS# bit in the MCR register. The CTS# input may be
used as a general purpose input when the modem in-
terface is not used.
MSR[5]: DSR Input Status
DSR#
(active high, logical 1). Normally this bit is the
compliment of the DSR# input. In the loopback mode,
this bit is equivalent to the DTR# bit in the MCR regis-
ter. The DSR# input may be used as a general pur-
pose input when the modem interface is not used.
MSR[6]: RI Input Status
RI# (active high, logical 1). Normally this bit is the
compliment of the RI# input. In the loopback mode
this bit is equivalent to bit-2 in the MCR register. The
RI# input may be used as a general purpose input
when the modem interface is not used.
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the
compliment of the CD# input. In the loopback mode
this bit is equivalent to bit-3 in the MCR register. The
CD# input may be used as a general purpose input
when the modem interface is not used.
6.11 I
NFRARED
T
RANSMIT
P
ULSE
W
IDTH
C
ONTROL
R
EGISTER
(IRPW) - W
RITE
O
NLY
The IRPW register allows the user to program the the
encoder’s pulse width. This cuts the LED on-time,
hence, reducing power consumption.
IRPW [7:0]: Pulse width control.
A 0x00 value (default) will set the pulse width to nor-
mal width of 3/16 of the data bit rate. The programma-
ble infrared pulse width can be calculated using the
following equation:
Infrared pulse width (PW) = Crystal clock period x ‘N’,
where ‘N’ is the value in IRPW from 1 to 255.
Examples:
Crystal frequency = 14.7456MHz (clock period of
67.82ns)
PW = 67.82 x ‘N’ or ranges from 67.82ns to 17.29ms
Caution: Never allow PW to exceed the operating da-
ta rate bit period, else the encoder stops.
6.12 S
CRATCH
P
AD
R
EGISTER
(SPR)
This is a 8-bit general purpose register for the user to
store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (de-
fault) after a reset or a power off-on cycle.
6.13 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM)
The concatenation of the contents of DLM and DLL
gives the 16-bit divisor value which is used to calcu-
late the baud rate:
Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
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