參數(shù)資料
型號(hào): XR16L651
廠商: Exar Corporation
英文描述: 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器(帶32字節(jié)先進(jìn)先出))
中文描述: 2.5V,3.3V與5V的低功耗的UART與32字節(jié)的FIFO(2.5伏,3.3伏和5V的低功耗通用異步接收器/發(fā)送器(帶32字節(jié)先進(jìn)先出))
文件頁數(shù): 31/46頁
文件大?。?/td> 516K
代理商: XR16L651
á
XR16L651
2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO
PRELIMINARY
REV. P1.0.0
31
with data in Xoff-2 register. If a match exists, the
received data will be transferred to FIFO and ISR
bit-4 will be set to indicate detection of the special
character. Bit-0 corresponds with the LSB bit for the
receive character. If flow control is set for compar-
ing Xon1, Xoff1 (EFR [1:0]=10) then flow control
and special character work normally. However, if
flow control is set for comparing Xon2, Xoff2
(EFR[1:0]=01) then flow control works normally, but
Xoff2 will not go to the FIFO, and will generate an
Xoff interupt and a special character interrupt.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control
by setting EFR bit-6 to logic 1. When Auto RTS is se-
lected, an interrupt will be generated when the re-
ceive FIFO is filled to the programmed trigger level
and RTS de-asserts to a logic 1 at the next upper trig-
ger level. RTS# will return to a logic 0 when FIFO da-
ta falls below the next lower trigger level. The RTS#
output must be asserted (logic 0) before the auto RTS
can take effect. RTS# pin will function as a general
purpose output when hardware flow control is dis-
abled.
Logic 0 = Automatic RTS flow control is disabled.
(default)
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled.
(default)
Logic 1 = Enable Automatic CTS flow control. Data
transmission stops when CTS# input de-asserts to
logic 1. Data transmission resumes when CTS#
input returns to a logic 0.
T
ABLE
13: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
XFR
Bits 7-0 = 0x00
MSR
Bits 3-0 = logic 0
Bits 7-4 = logic levels of the inputs
IRPW
Bits 7-0 = 0x00
SPR
Bits 7-0 = 0xFF
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX
Normal = logic 1
Infrared = logic 0
RTS#
Logic 1
DTR#
Logic 1
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