
XR16L651
2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO
REV. P1.0.0
á
PRELIMINARY
14
5.2
When software flow control is enabled (See
Table 12), the 651 compares compares one or two
sequential receive data characters with the pro-
grammed Xon or Xoff-1,2 character value(s). If re-
ceive character(s) (RX) match the programmed val-
ues, the 651 will halt transmission (TX) as soon as
the current character has completed transmission.
When a match occurs, the Xoff (if enabled via IER
bit-5) flag will be set and the interrupt output pin will
be activated. Following a suspension due to a match
of the Xoff characters values, the 651 will monitor the
receive data stream for a match to the Xon-1,2 char-
acter value(s). If a match is found, the 651 will re-
sume operation and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit
flow control registers to a logic 0. Following reset the
user can write any Xon/Xoff value desired for soft-
ware flow control. Different conditions can be set to
detect Xon/Xoff characters (See Table 12) and sus-
A
UTOMATIC
S
OFTWARE
F
LOW
C
ONTROL
pend/resume transmissions. When double 8-bit Xon/
Xoff characters are selected, the 651 compares two
consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and
controls TX transmissions accordingly. Under the
above described flow control mechanisms, flow con-
trol characters are not placed (stacked) in the user
accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and
flow control needs to be executed, the 651 automati-
cally sends an Xoff message (when enabled) via the
serial TX output to the remote modem. The 651
sends the Xoff-1,2 characters two-character-times (=
time taken to send two characters at the programmed
baud rate) after the receive FIFO crosses the pro-
grammed trigger level. To clear this condition, the 651
will transmit the programmed Xon-1,2 characters as
soon as receive FIFO drops to one trigger level below
the programmed trigger level. Table 4 below explains
this:
* After the trigger level is reached, an xoff character is sent after a short span of time ( = time required to send 2
characters); for example, after 2.083ms has elasped for 9600 baud and 10-bit word length setting.
5.3
S
PECIAL
C
HARACTER
D
ETECT
A special character detect feature is provided to de-
tect an 8-bit character when bit-5 is set in the En-
hanced Feature Register (EFR). When this charac-
ter (Xoff2) is detected, it will be placed in the FIFO
along with normal incoming RX data.
The 651 compares each incoming receive character
with Xoff-2 data. If a match exists, the received data
will be transferred to FIFO and ISR bit-4 will be set to
indicate detection of special character. Although the
Internal Register Table shows each X-Register with
eight bits of character information, the actual number
of bits is dependent on the programmed word length.
Line Control Register (LCR) bits 0-1 defines the num-
ber of character bits, i.e., either 5 bits, 6 bits, 7 bits, or
8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the
special character comparison. Bit-0 in the X-registers
corresponds with the LSB bit for the receive charac-
ter.
5.4
The 651 UART includes the infrared encoder and de-
coder compatible to the IrDA (Infrared Data Associa-
tion) version 1.0. The input pin ENIR conveniently ac-
tivates the infrared mode. Activating the ENIR pin pri-
or to power up prevents the infrared light emitting di-
ode (LED) from turning on and drawing large amount
of supply current while the system is powering up.
The ENIR pin also sets the MCR register bit-6 to a ‘1.
After power up or a reset, the software can overwrite
MCR bit-6 if so desired. In the infrared mode, the user
can choose to send/receive data either half-duplex or
full-duplex. The half-duplex mode is chosen by setting
bit-0 of XFR register to a ‘1’.
This prevents echoed
data from reaching the receiver. When the infrared
feature is enabled, the transmit data outputs, TX,
idles at logic zero level. Likewise, the RX input as-
sumes an idle level of logic zero, see Figure 10.
The IrDA standard defines the infrared encoder sends
out a
3/16 of a bit wide HIGH-pulse for each “0” bit in
the transmit data stream. This signal encoding reduc-
I
NFRARED
M
ODE
T
ABLE
4: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
RX T
RIGGER
L
EVEL
INT P
IN
A
CTIVATION
X
OFF
C
HARACTER
(
S
) S
ENT
(
CHARACTERS
IN
RX
FIFO
)
X
ON
C
HARACTER
(
S
) S
ENT
(
CHARACTERS
IN
RX
FIFO
)
8
8
8*
16*
24*
28*
0
8
16
24
28
16
24
28
16
24