參數(shù)資料
型號(hào)： XR16L651
廠商： Exar Corporation
英文描述： 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）)
中文描述： 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出））
文件頁(yè)數(shù)： 21/46頁(yè)
文件大?。?/td> 516K
代理商： XR16L651
á
XR16L651
2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO
PRELIMINARY
REV. P1.0.0
21
5.11 R
ECEIVER
The receiver section contains an 8-bit Receive Shift
Register (RSR) and 32 bytes of FIFO which includes
a byte-wide Receive Holding Register (RHR). The
RSR uses the 16X clock for timing. It verifies and vali-
dates every bit on the incoming character in the mid-
dle of each data bit. On the falling edge of a start or
false start bit, an internal receiver counter starts
counting at the 16X clock rate. After 8 clocks the start
bit period should be at the center of the start bit. At
this time the start bit is sampled and if it is still a logic
0 it is validated. Evaluating the start bit in this manner
prevents the receiver from assembling a false charac-
ter. The rest of the data bits and stop bits are sam-
pled and validated in this same manner to prevent
false framing. If there were any error(s), they are re-
ported in the LSR register bits 1- 4. Upon unloading
the receive data byte from RHR, the receive FIFO
pointer is bumped and the error flags are immediately
updated to reflect the status of the data byte in RHR
register. RHR can generate a receive data ready in-
terrupt upon receiving a character or delay until it
reaches the FIFO trigger level. Furthemore, data de-
livery to the host is guaranteed by a receive data
ready time-out function when receive data does not
reach the receive FIFO trigger level. This time-out de-
lay is 4 word lengths as defined by LCR[1,0] plus 12
bits time. The RHR interrupt is enabled by IER bit-0.
6.0
6.1
The receive holding register is a 8-bit register that
holds a receive data byte from the receive shift regis-
ter. It provides the receive data interface to the host
processor. The host reads the receive data byte on
this register whenever a data byte is trasferred from
the RSR. The RHR register is part of the receive
FIFO of 32 bytes by 11-bit wide, the 3 extra bits are
for the 3 error flags to be reported in LSR register.
When the FIFO is enabled by FCR bit-0, it acts as the
first-out register of the FIFO as new data are put over
the first-in register. Every time a read operation is
made to the receive holding register, its FIFO data
pointer is automatically bumped to the next sequential
data location. Also, the error flags associated with the
data byte are immediately updated onto the line sta-
tus register (LSR) bits 2-4.
6.2
B
AUD
R
ATE
G
ENERATOR
D
IVISORS
(DLL
AND
DLM)
The Baud Rate Generator (BRG) is a 16-bit counter
that generates the data rate for the transmitter. The
rate is programmed through registers DLL and DLM
which are only accessible when LCR bit-7 is set to ‘1’.
See Programmable Baud Rate Generator section for
more details.
REGISTERS
R
ECEIVE
H
OLDING
R
EGISTER
(RHR)
F
IGURE
13. T
RANSMIITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the selected Trigger
Level and then when
becomes empty. FIFO is
Enabled by FCR bit-0=1
Transmit
FIFO
(32-Byte)
TXFIFO1
16X Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
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