參數(shù)資料
型號： XR16L651
廠商： Exar Corporation
英文描述： 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）)
中文描述： 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出））
文件頁數(shù)： 19/46頁
文件大?。?/td> 516K
代理商： XR16L651
á
XR16L651
2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO
PRELIMINARY
REV. P1.0.0
19
5.10 T
RANSMITTER
The transmitter section comprises of
an 8-bit Trans-
mit Shift Register (TSR) and 32 bytes of FIFO which
includes a byte-wide Transmit Holding Register
(THR). THR receives a data byte from the host (non-
FIFO mode) or a data byte from the FIFO
when the
FIFO is enabled by FCR bit-0. TSR shifts out every
data bit with the 16X internal clock. A bit time is 16
clock periods. The transmitter sends the start-bit fol-
lowed by the number of data bits, inserts the proper
parity-bit if enabled, and adds the stop-bit(s). The sta-
tus of the THR and TSR are reported in the Line Sta-
tus Register (LSR bit-5 and bit-6).
5.10.1 Transmit Holding Register (THR)
The transmit holding register is an 8-bit register pro-
viding a data interface to the host processor. The host
writes transmit data byte to the THR to be converted
into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-
0) becomes first data bit to go out. The THR is the in-
put register to the transmit FIFO of 32 bytes when
FIFO operation is enabled by FCR bit-0. Every time a
write operation is made to the THR, its FIFO data
pointer is automatically bumped to the next sequential
data location. A THR empty interrupt can be generat-
ed when IER bit-1 is set to logic 1.
5.10.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at
a time. The THR empty flag (LSR bit-5) is set when
the data byte is transferred to TSR. THR flag can
generate a transmit empty interrupt (ISR bit-1) when
it is enabled by IER bit-1. The TSR flag (LSR bit-6) is
set when TSR becomes completely empty.
Enhanced Registers
0 0 1
EFR
R/W
Auto
CTS
Enable
Auto
RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
MSR[7:4]
IRPW[7:0]
XTRA[7:0]
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0xBF
1 0 0
XOFF1
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0xBF
1 0 1
XOFF2
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0xBF
1 1 0
XON1
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0xBF
1 1 1
XON2
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0xBF
T
ABLE
8: UART CONFIGURATION REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1.
A
DDRESS
A2-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
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