參數(shù)資料
型號： XR16L651
廠商： Exar Corporation
英文描述： 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）)
中文描述： 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出））
文件頁數(shù)： 45/46頁
文件大?。?/td> 516K
代理商： XR16L651
á
XR16L651
2.5, 3.3 AND 5.0V UART
PRELIMINARY
REV. P1.0.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
F
EATURES
................................................................................................................................................ 1
A
PPLICATIONS
........................................................................................................................................... 1
Figure 1. Block Diagram ......................................................................................................................... 1
Figure 2. Intel, Motorola and PC mode Pin Out. .................................................................................... 2
ORDERING
INFORMATION
........................................................................................................................... 2
PIN DESCRIPTIONS ........................................................................................................ 3
PRODUCT DESCRIPTION ............................................................................................... 6
FUNCTIONAL DESCRIPTIONS ............................................................................................................. 7
1.0 Host DATA BUS Interface ..................................................................................................................... 7
Figure 3. XR16L651 Intel Bus Interconnections .................................................................................... 7
Figure 4. XR16L651 Motorola Bus Interconnections. ............................................................................ 8
Figure 5. XR16L651 PC Mode Interconnections .................................................................................... 8
T
ABLE
1: PC M
ODE
I
NTERFACE
O
N
-
CHIP
A
DDRESS
D
ECODER
AND
I
NTERRUPT
S
ELECTION
. ....................... 9
Figure 6. PC Mode Interface in an Embedded Application. ................................................................... 9
2.0 INTERRUPT .......................................................................................................................................... 10
T
ABLE
2: I
NTERRUPT
O
UTPUT
(INT, INT#
AND
IRQA) F
UNCTIONS
.......................................................... 10
3.0 Crystal Oscillator or External Clock. ................................................................................................. 11
Figure 7. Typical oscillator connections ............................................................................................... 11
Figure 8. Baud Rate Generator ............................................................................................................ 11
T
ABLE
3: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
............................... 12
4.0 TRANSMIT AND RECEIVE DATA ....................................................................................................... 12
5.0 Automatic RTS Hardware Flow Control Operation .......................................................................... 12
Figure 9. Auto RTS and CTS Flow Control Operation ......................................................................... 13
T
ABLE
4: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
........................................................................ 14
Figure 10. Infrared Transmit Data Encoding and Receive Data Decoding .......................................... 15
T
ABLE
5: -RXRDY
PIN
........................................................................................................................... 15
T
ABLE
6: -TXRDY
PIN
........................................................................................................................... 15
Figure 11. Internal Loop Back .............................................................................................................. 16
T
ABLE
7: XR16L651 UART CONFIGURATION REGISTERS .............................................................. 17
T
ABLE
8: UART CONFIGURATION REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR
B
IT
-4=1. ................................................................................................................................................. 18
Figure 12. Transmitter Operation in non-FIFO Mode ........................................................................... 20
Figure 13. Transmiitter Operation in FIFO and Flow Control Mode ..................................................... 21
6.0 Registers .............................................................................................................................................. 21
Figure 14. Receiver Operation in non-FIFO Mode ............................................................................... 22
Figure 15. Receiver Operation in FIFO and Auto RTS Flow Control Mode ......................................... 22
T
ABLE
9: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
................................................................................ 24
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
WITH
AUTO
RTS
HYSTERESIS
........ 25
T
ABLE
11: P
ARITY
SELECTION
................................................................................................................ 26
T
ABLE
12: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
................................................................................ 30
T
ABLE
13: UART RESET CONDITIONS .............................................................................................. 31
A
BSOLUTE
M
AXIMUM
R
ATINGS
.......................................................................................................... 32
ELECTRICAL CHARACTERISTICS (PRELIMINARY) .................................................. 32
DC E
LECTRICAL
C
HARACTERISTICS
FOR
2.5V S
IGNALING
........................................................................ 32
AC E
LECTRICAL
C
HARACTERISTICS
FOR
2.5V S
IGNALLING
....................................................................... 33
DC E
LECTRICAL
C
HARACTERISTICS
FOR
3.3V S
IGNALING
........................................................................ 34
AC E
LECTRICAL
C
HARACTERISTICS
FOR
3.3V S
IGNALING
......................................................................... 35
DC E
LECTRICAL
C
HARACTERISTICS
FOR
5.0V S
IGNALING
........................................................................ 36
AC E
LECTRICAL
C
HARACTERISTICS
FOR
5.0V S
IGNALING
......................................................................... 37
Figure 16. InteL Data Bus Read and Write Timing .............................................................................. 38
Figure 17. Motorola Data Bus Read and Write Timing ........................................................................ 39
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