參數(shù)資料
型號： XR16L651
廠商： Exar Corporation
英文描述： 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）)
中文描述： 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出））
文件頁數(shù)： 16/46頁
文件大?。?/td> 516K
代理商： XR16L651
XR16L651
2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO
REV. P1.0.0
á
PRELIMINARY
16
ister input allowing the system to receive the same
data that it was sending. The TX pin is held at logic 1
or mark condition while RTS# and DTR# are de-as-
serted, and CTS#, DSR# CD# and RI# inputs are ig-
nored.
5.7
D
EVICE
I
DENTIFICATION
AND
R
EVISION
The XR16L651 provides a Device Identification code
and a Device Revision code to distinguish the part
from others. To read the identification code from the
part, it is required to set the baud rate generator reg-
isters DLL and DLM both to 0x00. Now, reading the
content of the DLM will provide 0x04 for the
XR16L651 and reading the content of DLL will pro-
vide the revision of the part; for example, a reading of
0x01 means revision A.
5.8
S
LEEP
M
ODE
& W
AKE
-
UP
I
NDICATOR
The 651 is designed to operate with low power con-
sumption. A special sleep mode is included to further
reduce power consumption when the chip is not be-
ing used. With EFR bit-4 and IER bit-4 enabled (set to
a logic 1), the 651 enters the sleep mode but re-
sumes normal operation when a start bit is detected,
a change of state on any of the modem input pins RX,
-RI, -CTS, -DSR, -CD, or transmit data is provided by
the user. If the sleep mode is enabled and the 651 is
awakened by one of the conditions described above,
an interrupt is issued by the 651 to signal to the CPU
that it is awake. The interrupt source register (ISR)
will read a value of 0x01 for this interrupt and reading
the ISR clears this interrupt. Since the same value is
also used to indicate no pending interrupt, users
should exercise caution while using the sleep mode.
Once awakened, the 651 will return to the sleep
mode automatically after any other interrupting condi-
tion (the true cause of waking up the 651) has been
serviced. In any case, the sleep mode will not be en-
tered while an interrupt is pending. The 651 will stay
in the sleep mode of operation until it is disabled by
setting IER bit-4 to a logic 0.
5.9
UART CONFIGURATION REGISTERS.
F
IGURE
11. I
NTERNAL
L
OOP
B
ACK
TX [7:0]
RX [7:0]
M
L
I
RTS# [7:0]
MCR bit-4=1
VCC
VCC
VCC
Transmit Shift
Register
Receive Shift
Register
CTS# [7:0]
DTR# [7:0]
DSR# [7:0]
RI# [7:0]
CD# [7:0]
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
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