參數(shù)資料
型號(hào): XR16L651
廠商: Exar Corporation
英文描述: 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器(帶32字節(jié)先進(jìn)先出))
中文描述: 2.5V,3.3V與5V的低功耗的UART與32字節(jié)的FIFO(2.5伏,3.3伏和5V的低功耗通用異步接收器/發(fā)送器(帶32字節(jié)先進(jìn)先出))
文件頁(yè)數(shù): 12/46頁(yè)
文件大?。?/td> 516K
代理商: XR16L651
XR16L651
2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO
REV. P1.0.0
á
PRELIMINARY
12
4.0
The 651 UART has a transmit holding register (THR)
and a receive holding register (RHR). The software
driver must first separately read the LSR content for
associated received data byte error flags before read-
ing the receive data byte off the register RHR. That is
because upon reading the RHR register the FIFO
pointer increments and points to next data byte.
4.1
FIFO
DATA LOADING AND UNLOADING
THROUGH REGISTERS THR AND RHR.
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift Reg-
ister (TSR). The status of the THR is provided in the
Line Status Register (LSR). Writing to the THR trans-
fers the contents of the data bus (D7-D0) to the THR,
providing that the THR or TSR is empty. The THR
empty flag in the LSR register will be set to a logic 1
when the transmitter is empty or when data is trans-
ferred to the TSR. Note that a write operation can be
performed when the transmit holding register empty
flag is set (logic 0 = at least one byte in FIFO / THR,
logic 1= FIFO/THR empty).
The serial receive section also contains an 8-bit Re-
ceive Holding Register, RHR. Receive data is unload-
ed by reading the RHR register. The receive section
provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal re-
ceiver counter starts counting clocks at 16x clock
rate. After 7 1/2 clocks the start bit time should be
TRANSMIT AND RECEIVE DATA
shifted to the center of the start bit. At this time the
start bit is sampled and if it is still a logic 0 it is validat-
ed. Evaluating the start bit in this manner prevents
the receiver from assembling a false character. Data
byte error, if any, status is reported in LSR register.
The THR and RHR register address is located at
0x00. Transmit data byte is loaded to the THR when
writting to address 0x00. Receive data is unloaded
from the RHR register when reading that same ad-
dress location.
5.0
AUTOMATIC RTS HARDWARE FLOW CON-
TROL OPERATION
Automatic RTS hardware flow control is used to pre-
vent data overrun to the local receiver FIFO. The
RTS# output is used to request remote unit to sus-
pend/resume data transmission. The auto RTS flow
control features is enabled to fit specific application
requirement (see Figure 9):
- Enable auto RTS flow control using EFR bit-6.
- The auto RTS function must be started by asserting
RTS output pin (MCR bit-0 or 1 to logic 1 after it is
enabled.
- Enable RTS interrupt through IER bit-6 (after setting
EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition: ISR bit-5 will be set to
logic 1.
With the Auto RTS function enabled, the RTS# pin will
not be de-asserted (logic 1) when the receive FIFO
T
ABLE
3: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
O
UTPUT
Data Rate
MCR Bit-7=1
O
UTPUT
Data Rate
MCR Bit-7=0
D
IVISOR
FOR
16x
Clock (Decimal)
D
IVISOR
FOR
16x
Clock (HEX)
DLM
P
ROGRAM
V
ALUE
(HEX)
DLL
P
ROGRAM
V
ALUE
(HEX)
D
ATA
R
ATE
E
RROR
(%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
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