XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
PRELIMINARY
REV. P1.0.1
142
The “HEC Byte Error Correction/Detection”
Algorithm
If the Receive Cell Processor detects one or more
errors in the header bytes of a given cell, then the
“HEC Byte Error Correction/Detection” algorithm will be
employed. The “HEC Byte Error Correction/Detection”
Algorithm has two states: Detection and Correction.
Figure 31 presents a State Machine Diagram of the
“HEC Byte Error Correction/Detection” Algorithm.
Each of these states are discussed below.
The “Correction” State
When the “HEC Byte Correction/Detection” Algorithm
is operating in the Correction Mode, cells with single
bit errors (within the header bytes) will be corrected.
However, cells with multiple bit errors are discarded,
unless configured by the user. To configure the Re-
ceive Cell Processor to retain these cells with multi-bit
errors, write to bit 0 (HEC Error Ignore) of the RxCP
Configuration Register, as depicted below.
Writing a “1” into this bit-field causes the Receive Cell
Processor to retain errored cells for further processing.
Writing a “0” to this bit-field causes the Receive Cell
Processor to discard those cells with multi-bit errors.
Note: The occurrence of any cells with header byte errors
(single-bit or multi-bit errors) will cause the Receive Cell
Processor to transition from the “Correction” state to the
“Detection” state.
RxCP Configuration Register (Address = 4Ch)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
RxLCD
RDPChk
Pattern
RDPChk
Pattern Enable
Idle Cell
Discard
OAM Check
Bit
De-Scramble
Enable
RxCoset
Enable
HEC Error
Ignore
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
x
x
x
x
x
x
x
F
IGURE
31. S
TATE
M
ACHINE
D
IAGRAM
OF
THE
HEC B
YTE
E
RROR
C
ORRECTION
/D
ETECTION
A
LGORITHM
Correction
Mode
Detection
Mode
No Error
Detected
Multi-bit Error Detected
(Cell Discarded)
No Error Detected
for M consecutive cells
Single-bit Error Detected
(Cell Corrected)
Error Detected
(Cell Discarded)
Alpha consecutive cells with incorrect
HEC bytes (to HUNT state)
RxCP Configuration Register (Address = 4Ch)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
RxLCD
RDPChk
Pattern
RDPChk
Pattern Enable
Idle Cell
Discard
OAM Check
Bit
De-Scramble
Enable
RxCoset
Enable
HEC Error
Ignore
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
x
x
x
x
x
x
x